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CS2000P-DZZR PDF预览

CS2000P-DZZR

更新时间: 2024-11-28 20:10:27
品牌 Logo 应用领域
凌云 - CIRRUS 光电二极管
页数 文件大小 规格书
30页 944K
描述
Phase Locked Loop, Hybrid, PDSO10, 3 MM, LEAD FREE, MO-187, MSOP-10

CS2000P-DZZR 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:TSSOP包装说明:TSSOP, TSSOP10,.19,20
针数:10Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.68
模拟集成电路 - 其他类型:PHASE LOCKED LOOPJESD-30 代码:S-PDSO-G10
长度:3 mm功能数量:1
端子数量:10最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP10,.19,20
封装形状:SQUARE封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
认证状态:Not Qualified座面最大高度:1.1 mm
子类别:PLL or Frequency Synthesis Circuits最大供电电流 (Isup):18 mA
最大供电电压 (Vsup):3.5 V最小供电电压 (Vsup):3.1 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:HYBRID温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3 mmBase Number Matches:1

CS2000P-DZZR 数据手册

 浏览型号CS2000P-DZZR的Datasheet PDF文件第2页浏览型号CS2000P-DZZR的Datasheet PDF文件第3页浏览型号CS2000P-DZZR的Datasheet PDF文件第4页浏览型号CS2000P-DZZR的Datasheet PDF文件第5页浏览型号CS2000P-DZZR的Datasheet PDF文件第6页浏览型号CS2000P-DZZR的Datasheet PDF文件第7页 
CS2000-OTP  
Fractional-N Clock Synthesizer & Clock Multiplier  
Features  
General Description  
Delta-Sigma Fractional-N Frequency Synthesis  
The CS2000-OTP is an extremely versatile system  
clocking device that utilizes a programmable phase lock  
loop. The CS2000-OTP is based on a hybrid analog-  
digital PLL architecture comprised of a unique combina-  
Generates a Low Jitter 6 - 75 MHz Clock  
from an 8 - 75 MHz Reference Clock  
Clock Multiplier / Jitter Reduction  
tion of  
a
Delta-Sigma Fractional-N Frequency  
Generates a Low Jitter 6 - 75 MHz Clock  
from a Jittery 50 Hz to 30 MHz Clock  
Source  
Synthesizer and a Digital PLL. This architecture allows  
for both frequency synthesis/clock generation from a  
stable reference clock as well as generation of a low-jit-  
ter clock relative to an external noisy synchronization  
clock with frequencies as low as 50 Hz. The CS2000-  
OTP has many configuration options which are set once  
prior to runtime. At runtime there are three hardware  
configuration pins available for mode and feature  
selection.  
Highly Accurate PLL Multiplication Factor  
Maximum Error Less Than 1 PPM in High-  
Resolution Mode  
One-Time Programmability  
Configurable Hardware Control Pins  
Configurable Auxiliary Output  
The CS2000-OTP is available in a 10-pin MSOP pack-  
age in Commercial (-10°C to +70°C) and Automotive-D  
(-40°C to +85°C) and Automotive-E (-40°C to +105°C)  
grades. Customer development kits are also available  
for custom device prototyping, small production pro-  
gramming, and device evaluation. Please see “Ordering  
Information” on page 29 for complete details.  
Flexible Sourcing of Reference Clock  
External Oscillator or Clock Source  
Supports Inexpensive Local Crystal  
Minimal Board Space Required  
No External Analog Loop-filter  
Components  
3.3 V  
Timing Reference  
Frequency Reference  
Hardware Control  
Hardware Configuration  
Auxiliary  
Output  
PLL Output  
Lock Indicator  
Fractional-N  
Frequency Synthesizer  
8 MHz to 75 MHz  
Low-Jitter Timing Reference  
6 to 75 MHz  
PLL Output  
N
Output to Input  
Clock Ratio  
50 Hz to 30 MHz  
Frequency Reference  
Digital PLL & Fractional  
N Logic  
Output to Input  
Clock Ratio  
Cirrus Logic Confidential  
Copyright Cirrus Logic, Inc. 2009–2015  
(All Rights Reserved)  
OCT '15  
DS758F3  
http://www.cirrus.com  

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