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CR16MNS944V9 PDF预览

CR16MNS944V9

更新时间: 2024-11-15 15:30:23
品牌 Logo 应用领域
美国国家半导体 - NSC 时钟微控制器外围集成电路
页数 文件大小 规格书
99页 444K
描述
IC 16-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PQCC44, PLASTIC, LCC-44, Microcontroller

CR16MNS944V9 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:QCCJ, LDCC44,.7SQReach Compliance Code:not_compliant
HTS代码:8542.31.00.01风险等级:5.92
具有ADC:YES地址总线宽度:
位大小:16CPU系列:CR16B
最大时钟频率:20 MHzDAC 通道:NO
DMA 通道:NO外部数据总线宽度:
JESD-30 代码:S-PQCC-J44JESD-609代码:e0
长度:16.5862 mm湿度敏感等级:2A
I/O 线路数量:33端子数量:44
最高工作温度:70 °C最低工作温度:
PWM 通道:YES封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC44,.7SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):220电源:5 V
认证状态:Not QualifiedRAM(字节):2048
ROM(单词):49152ROM可编程性:FLASH
座面最大高度:4.57 mm速度:20 MHz
子类别:Microcontrollers最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:16.5862 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER, RISC
Base Number Matches:1

CR16MNS944V9 数据手册

 浏览型号CR16MNS944V9的Datasheet PDF文件第2页浏览型号CR16MNS944V9的Datasheet PDF文件第3页浏览型号CR16MNS944V9的Datasheet PDF文件第4页浏览型号CR16MNS944V9的Datasheet PDF文件第5页浏览型号CR16MNS944V9的Datasheet PDF文件第6页浏览型号CR16MNS944V9的Datasheet PDF文件第7页 
December 2001  
CR16MES5/CR16MES9/CR16MFS5/CR16MFS9/  
CR16MHS5/CR16MHS9/CR16MNS5/CR16MNS9/  
CR16M9S5/CR16MUS5/CR16MUS9/  
Family of CompactRISC 16-Bit Microcontrollers  
1.0 General Description  
The family of CompactRISC™ microcontrollers are gener-  
al-purpose 16-bit microcontrollers based on a Reduced In-  
struction Set Computer (RISC) architecture. The device  
operates as a complete microcomputer with all system tim-  
ing, interrupt logic, flash program memory or ROM memo-  
ry, RAM, EEPROM data memory, and I/O ports included  
on-chip. It is ideally suited to a wide range of embedded  
controller applications because of its high performance,  
on-chip integrated features and low power consumption,  
resulting in decreased system cost.  
The family of CompactRISC 16-bit microcontrollers offer  
the high performance of a RISC architecture while retain-  
ing the advantages of a traditional Complex Instruction Set  
Computer (CISC): compact code, on-chip memory and I/O,  
and reduced cost. The CPU uses a three-stage instruction  
pipeline that allows execution of up to one instruction per  
clock cycle, or up to 20 million instructions per second (MI-  
PS) at a clock rate of 20 MHz.  
Block Diagram  
Fast Osc Slow Osc  
Processing  
CR16B  
Unit  
Core  
Clock Generator  
Power-on-Reset  
Core Bus  
640 Bytes  
EEPROM  
Data  
Peripheral  
Bus  
Controller  
Interrupt  
Control  
(ICU)  
Power-Save  
Management  
48k Flash  
Program  
Memory  
2 kbyte  
RAM  
boot  
ROM  
WATCHDOG  
Memory  
Peripheral Bus  
Two  
MFTs  
Two  
USARTs  
Two Analog  
Comparators  
Real-Time  
Timer  
I/O  
A/D  
MIWU  
mWire/SPI  
Please note that not all family members contain same peripheral modules and features.  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
©2001 National Semiconductor Corporation  
www.national.com  

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