3.20
DMA CONTROLLER
3.21
SERIAL DEBUG INTERFACE
The Direct Memory Access Controller (DMAC) can speed The Serial Debug Interface module (SDI module) provides
up data transfer between memory and I/O devices or be- a JTAG-based serial link to an external debugger, for exam-
tween two memories, relative to data transfers performed di- ple running on a PC. In addition, the SDI module integrates
rectly by the CPU. A method called cycle-stealing allows the an on-chip debug module, which allows the user to set up to
CPU and the DMAC to share the CPU bus efficiently. The eight hardware breakpoints on instruction execution and
DMAC implements four independent DMA channels. DMA data transfer. The SDI module can act as a CPU bus master
requests from a primary and a secondary source are recog- to access all memory mapped resources, such as RAM and
nized for each DMA channel, as well as a software DMA re- peripherals. Therefore it also allows for fast program code
quest issued directly by the CPU. Table 1 shows the DMA download into the on-chip Flash program memory using the
channel assignment on the CP3CN23 architecture. The fol- JTAG interface.
lowing on-chip modules can assert a DMA request to the
DMAC:
3.22
DEVELOPMENT SUPPORT
In addition to providing the features needed for the next gen-
eration of embedded products, the CP3CN23 devices are
backed up by the software resources designers need for
rapid product development, including an operating system,
peripheral drivers, reference designs, and an integrated de-
velopment environment.
•
•
•
•
CR16C (Software DMA request)
USART
Advanced Audio Interface
CVSD/PCM Converter
Table 1 shows how the four DMA channels are assigned
to the modules listed above.
National Semiconductor offers a complete and industry-
proven application development environment for CP3CN23
applications, including the IAR Embedded Workbench,
iSYSTEM winIDEA and iC3000 Active Emulator, and Appli-
cation Software. See your National Semiconductor sales
representative for current information on availability and fea-
tures of emulation equipment and evaluation boards.
Table 1 DMA Channel Assignment
Primary/
Secondary
Channel
Peripheral
Transaction
Primary
Secondary
Primary
Reserved
UART0
Read/Write
Read
Write
0
UART0
1
2
3
Secondary
Primary
Unused
AAI
N/A
Read
Read
Write
Secondary
Primary
CVSD/PCM
AAI
Secondary
CVSD/PCM
Write
The interface can handle data words of either 8- or 16-bit
length and data frames can consist of up to four slots.
In the normal mode of operation, the interface only transfers
one word at a periodic rate. In the network mode, the inter-
face transfers multiple words at a periodic rate. The periodic
rate is also called a data frame and each word within one
frame is called a slot. The beginning of each new data frame
is marked by the frame sync signal.
7
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