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CP3CN23

更新时间: 2022-04-23 23:00:11
品牌 Logo 应用领域
美国国家半导体 - NSC /
页数 文件大小 规格书
246页 3536K
描述
CP3CN23 Reprogrammable Connectivity Processor with Dual CAN Interfaces

CP3CN23 数据手册

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3.7  
CAN INTERFACE  
3.11  
12-BIT ANALOG TO DIGITAL  
CONVERTER  
Two CAN modules provide Full CAN 2.0B class, CAN serial  
bus interface for applications that require a high-speed (up  
to 1 Mbits per second) or a low-speed interface with CAN  
bus master capability. The data transfer between CAN and  
the CPU is established by 15 memory-mapped message  
buffers, which can be individually configured as receive or  
transmit buffers. An incoming message is filtered by two  
masks, one for the first 14 message buffers and another one  
for the 15th message buffer to provide a basic CAN path. A  
priority decoder allows any buffer to have the highest or low-  
est transmit priority. Remote transmission requests can be  
processed automatically by automatic reconfiguration to a  
receiver after transmission or by automated transmit sched-  
uling upon reception. In addition, a time stamp counter (16-  
bits wide) is provided to support real-time applications.  
This device contains an 8-channel, multiplexed input, suc-  
cessive approximation, 12-bit Analog-to-Digital Converter. It  
supports both Single Ended and Differential modes of oper-  
ation.  
The integrated 12-bit ADC provides the following features:  
„ 8-channel, multiplexed input  
„ 4 differential channels  
„ Single-ended and differential external filtering capability  
„ 12-bit resolution; 11-bit accuracy  
„ 15-microsecond conversion time  
„ Support for 4-wire touchscreen applications  
„ External start trigger  
„ Programmable start delay after start trigger  
„ Poll or interrupt on done  
The CAN modules are fast core bus peripherals, which al-  
low single-cycle byte or word read/write access. A set of di-  
agnostic features (such as loopback, listen only, and error  
identification) support the development with the CAN mod-  
ule and provide a sophisticated error management tool.  
The ADC is compatible with 4-wire resistive touchscreen  
applications and is intended to provide the resolution neces-  
sary to support handwriting recognition. Low-ohmic touch-  
screen drivers are provided internally on the ADC[3:0] pins.  
Pendown detection is also provided.  
The CAN receivers can trigger a wake-up condition out of  
the low-power modes through the Multi-Input Wake-Up  
module.  
The ADC provides several options for the voltage reference  
source. The positive reference can be ADVCC (internal),  
VREFP, ADC0, or ADC3. The negative reference can be  
ADVCC (internal), ADC1, or ADC2.  
3.8  
QUAD UART  
Four UART modules support a wide range of programmable  
baud rates and data formats, parity generation, and several  
error detection schemes. The baud rate is generated on-  
chip, under software control. One UART channel supports  
hardware flow control, DMA, and USART capability (syn-  
chronous mode).  
Two specific analog channel selection modes are support-  
ed. These are as follows:  
„ Allow any specific channel to be selected at one time.  
The A/D Converter performs the specific conversion re-  
quested and stops.  
„ Allow any differential channel pair to be selected at one  
time. The A/D Converter performs the specific differential  
conversion requested and stops.  
The UARTs offer a wake-up condition from the low-power  
modes using the Multi-Input Wake-Up module.  
In both Single-Ended and Differential modes, there is the  
capability to connect the analog multiplexer output and A/D  
converter input to external pins. This provides the ability to  
externally connect a common filter/signal conditioning cir-  
cuit for the A/D Converter.  
3.9  
ADVANCED AUDIO INTERFACE  
The audio interface provides a serial synchronous, full-du-  
plex interface to CODECs and similar serial devices. Trans-  
mit and receive paths operate asynchronously with respect  
to each other. Each path uses three signals for communica-  
tion: shift clock, frame synchronization, and data.  
3.12  
RANDOM NUMBER GENERATOR  
When the receiver and transmitter use separate shift clocks  
and frame sync signals, the interface operates in its asyn-  
chronous mode. Alternatively, the transmit and receive path  
can share the same shift clock and frame sync signals for  
synchronous mode operation.  
RNG peripheral for use in Trusted Computer Peripheral Ap-  
plications (TCPA) to improve the authenticity, integrity, and  
privacy of Internet-based communication and commerce.  
3.10  
CVSD/PCM CONVERSION MODULE  
The CVSD/PCM module performs conversion between  
CVSD data and PCM data, in which the CVSD encoding is  
as defined in the Bluetooth specification and the PCM data  
can be 8-bit µ-Law, 8-bit A-Law, or 13-bit to 16-bit Linear.  
5
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