uling upon reception. In addition, a time stamp counter (16-
bits wide) is provided to support real time applications.
3.17
ADVANCED AUDIO INTERFACE
The audio interface provides a serial synchronous, full-du-
plex interface to codecs and similar serial devices. Transmit
and receive paths operate asynchronously with respect to
each other. Each path uses three signals for communica-
tion: shift clock, frame synchronization, and data.
The CAN module is a fast core bus peripheral, which allows
single cycle byte or word read/write access. A set of diag-
nostic features (such as loopback, listen only, and error
identification) support the development with the CAN mod-
ule and provide a sophisticated error management tool.
In case receive and transmit use separate shift clocks and
frame sync signals, the interface operates in its asynchro-
nous mode. Alternatively, the transmit and receive path can
share the same shift clock and frame sync signals for syn-
chronous mode operation.
The CAN receiver can trigger a wake-up condition out of the
low-power modes through the Multi-Input Wake-Up module.
3.15
ACCESS.BUS INTERFACE
The ACCESS.bus interface module (ACB) is a two-wire se-
rial interface with the ACCESS.bus physical layer. It is also
compatible with Intel’s System Management Bus (SMBus)
and Philips’ I2C bus. The ACB module can be configured as
a bus master or slave, and can maintain bidirectional com-
munications with both multiple master and slave devices.
The interface can handle data words of either 8- or 16-bit
length and data frames can consist of up to four slots.
In the normal mode of operation, the interface only transfers
one word at a periodic rate. In the network mode, the inter-
face transfers multiple words at a periodic rate. The periodic
rate is also called a data frame and each word within one
frame is called a slot. The beginning of each new data frame
is marked by the frame sync signal.
The ACCESS.bus receiver can trigger a wake-up condition
out of the low-power modes using the Multi-Input Wake-Up
module.
3.18
CVSD/PCM CONVERSION MODULE
3.16
DMA CONTROLLER
The CVSD/PCM module performs conversion between
CVSD and PCM data, in which the CVSD encoding is as de-
fined in the Bluetooth specification 1.0 and the PCM data
can be 8-bit µ-Law, 8-bit A-Law, or 13-bit to 16-bit Linear.
The Direct Memory Access Controller (DMAC) can speed
up data transfer between memory and I/O devices or be-
tween two memories, relative to data transfers performed di-
rectly by the CPU. A method called cycle-stealing allows the
CPU and the DMAC to use the core bus in parallel. The
DMAC implements four independent DMA channels. DMA
requests from a primary and a secondary source are recog-
nized for each DMA channel, as well as a software DMA re-
quest issued directly by the CPU. Table 1 shows the DMA
channel assignment on the CP3CN17 architecture. The fol-
lowing on-chip modules can assert a DMA request to the
DMAC:
3.19
SERIAL DEBUG INTERFACE
The Serial Debug Interface module (SDI module) provides
a JTAG-based serial link to an external debugger, for exam-
ple running on a PC. In addition, the SDI module integrates
an on-chip debug module, which allows the user to set up to
four hardware breakpoints on instruction execution and data
transfer. The SDI module can act as a CPU bus master to
access all memory mapped resources, such as RAM and
peripherals. It also provides fast program download into the
on-chip Flash program memory using the JTAG interface.
CR16C (Software DMA request)
UART
Advanced Audio Interface
CVSD/PCM Converter
Note: The SDI module may assert Freeze mode to gather
information, which may cause periodic fluctuations in re-
sponse (bus availability, interrupt latency, etc.). Anomalous
behavior often may be traced to SDI activity.
Table 1 shows how the four DMA channels are assigned
to the modules listed above.
3.20
DEVELOPMENT SUPPORT
Table 1 DMA Channel Assignment
The CP3CN17 is backed up by the software resources de-
signers need for rapid time-to-market, including an operat-
ing system, peripheral drivers, reference designs, and an
integrated development environment.
Primary/
Secondary
Channel
Peripheral
Transaction
Primary
Secondary
Primary
Reserved
UART
N/A
Read
Write
N/A
National Semiconductor offers a complete and industry-
proven application development environment for CP3CN17
applications, including the IAR Embedded Workbench,
iSYSTEM winIDEA and iC3000 Active Emulator, Develop-
ment Board, and Application Software. See your National
Semiconductor sales representative for current information
on availability and features of emulation equipment and
evaluation boards.
0
UART
1
2
3
Secondary
Primary
Unused
AAI
Read
Read
Write
Write
Secondary
Primary
CVSD/PCM
AAI
Secondary
CVSD/PCM
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