August 2000
COP820C/840C Family
8-Bit CMOS ROM Based Microcontrollers with 1k or 2k
Memory
sions are available (COP87LxxCJ/RJ Family). Erasable win-
dowed versions are available for use with a range of COP8
software and hardware development tools.
General Description
Note: COP8SA devices are instruction set and pinout com-
patible supersets of the COP800C Family devices, and are
Family features include an 8-bit memory mapped architec-
replacements for these in new designs when possible.
ture, 10 Hz CKI with 1µs instruction cycle, one multi-function
The COP820C/840C Family ROM based microcontrollers
™
16-bit timer/counter with PWM, MICROWIRE/PLUS serial
™
are integrated COP8
Base core devices with smaller
I/O, power saving HALT mode, three clock modes, high cur-
rent outputs, software selectable I/O options, 2.3v-6.0v op-
eration and 20/28 pin packages.
memory (1k/2k), and fewer on-board features. These single-
chip CMOS devices are suited for lower-functionality appli-
cations where system cost is of prime consideration. Pin and
software compatible (different VCC range) 4k/32k OTP ver-
Devices included in this datasheet are:
Device
Memory (bytes)
RAM
(bytes)
64
I/O Pins
Packages
Temperature
Comments
COP620C
COP820C
COP920C
1k ROM
1k ROM
1k ROM
24
24
24
28 DIP/SOIC
28 DIP/SOIC
28 DIP/SOIC
-55 to +125˚C
-40 to +85˚C
0 to +70˚C
4.5v - 5.5v
64
64
2.3v-4.0v,
CH=4.0v-6.0v
COP622C
COP822C
COP922C
1k ROM
1k ROM
1k ROM
64
64
64
16
16
16
20 DIP/SOIC
20 DIP/SOIC
20 DIP/SOIC
-55 to +125˚C
-40 to +85˚C
0 to +70˚C
4.5v - 5.5v
2.3v-4.0v,
CH=4.0v-6.0v
COP640C
COP840C
COP940C
2k ROM
2k ROM
2k ROM
128
128
128
24
24
24
28 DIP/SOIC
28 DIP/SOIC
28 DIP/SOIC
-55 to +125˚C
-40 to +85˚C
0 to +70˚C
4.5v - 5.5v
2.3v-4.0v,
CH=4.0v-6.0v
COP642C
COP842C
COP942C
2k ROM
2k ROM
2k ROM
128
128
128
16
16
16
20 DIP/SOIC
20 DIP/SOIC
20 DIP/SOIC
-55 to +125˚C
-40 to +85˚C
0 to +70˚C
4.5v - 5.5v
2.3v-4.0v,
CH=4.0v-6.0v
— 20 DIP/SO with 16 I/O pins
— 28 DIP/SO with 24 I/O pins
Key Features
n 16-bit multi-function timer supporting
— PWM mode
CPU/Instruction Set Feature
n 1 µs instruction cycle time
— External event counter mode
— Input capture mode
n Three multi-source interrupts servicing
— External interrupt with selectable edge
— Timer interrupt
n 1024 bytes ROM/64 bytes RAM-COP820C
n 2048 bytes ROM/128 bytes RAM-COP840C
— Software interrupt
I/O Features
n Versatile and easy to use instruction set
n 8-bit Stack point (SP)—stack in RAM
n Two 8-bit Register Indirect Memory Pointers (B, X)
n Memory mapped I/O
n Software selectable I/O options (TRI-STATE® Output,
Push-Pull Output, Weak Pull-Up Input, High Impedance
Input)
Fully Static CMOS
n Low current drain (typically 1 µA)
n Single supply operation: 2.5V to 6.0V
n High current outputs
<
n Schmitt trigger inputs on Port G
n MICROWIRE/PLUS serial I/O
n Packages:
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
™
™
™
COP8 , MICROWIRE and MICROWIRE/PLUS are trademarks of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation
DS009103
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