CM8888-2

更新时间： 2024-01-15 17:49:37

品牌	Logo	应用领域
CALMIRCO		/
页数	文件大小	规格书
13页	322K
描述
CMOS INTEGRATED DTMF TRANCEIVER

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CM8888-2 技术参数

生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOP,	针数：	20
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.82	Is Samacsys：	N
JESD-30 代码：	R-PDSO-G20	长度：	12.905 mm
功能数量：	1	端子数量：	20
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
认证状态：	Not Qualified	座面最大高度：	2.85 mm
最大压摆率：	10 mA	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
电信集成电路类型：	DTMF SIGNALING CIRCUIT	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	宽度：	7.635 mm
Base Number Matches：	1

CM8888-2 数据手册

CALIFORNIA MICRO DEVICES

CM8888/8888-2

Receiver Section

Separation of the low and high group tones is

achieved by applying the DTMF signal to the inputs to

two sixth order switched capacitor bandpass filters, the

bandwidths of which correspond to the low and high-

group frequencies as shown in Figure 5. The low-

group filter incorporates notches at 350 Hz and 440

Hz for excellent dial-tone rejection. Each filter output

is followed by a single-order switched capacitor filter

section which smoothes the signals prior to limiting.

Limiting is performed by high-gain comparators with

hysteresis to prevent detection of unwanted low-level

signals. The outputs of the comparators provide full-

rail logic swings at the incoming DTMF signals

frequencies.

checks for a valid signal duration (referred to as

Character Recognition Condition). This check is

performed by an external RC time constant driven by

ESt. A logic high on ESt causes VC (See Figure 3) to

rise as the capacitor discharge. Provided that the

signal condition is maintained (ESt remains high) for

the validation period (tGTP), VC reaches the threshold

(VTSt) of the steering logic to register the tone pair,

latching its corresponding 4-bit code (See Figure 5)

into the Receive Data Register. At this point the GT

continues to drive high as long as ESt remains high.

Finally, after a short delay to allow the output latch to

settle, the Delayed Steering output flag goes high,

signalling that a received tone pair has been registered.

It is possible to monitor the status of the Delayed

Steering flag by checking the appropriate bit in the

Status Register. If Interrupt Mode has been selected,

the IRQ/CP pin will pull low when the Delayed Steering

flag is active.

Following the filter section is a decoder which employs

digital counting techniques to determine the

frequencies of the incoming tones, and to verify that

the incoming tones correspond to standard DTMF

frequencies. A complex averaging algorithm protects

against tone simulation by extraneous signals (e.g.

voice), while still providing tolerance to small

deviations in frequency. The averaging algorithm was

developed to ensure and optimum combination of

immunity to talk-off , as well as a tolerance to the

presence of two valid tones (sometimes referred to as

signal condition in industry publications), the Early

Steering (EST) output will go to and active state. Any

subsequent loss of signal condition will cause ESt to

assume and inactive state.

The contents of the output latch are updated on an active

Delayed Steering transition. This data is presented to the

4-bit bi directional data bus when the Receive Data

validate the interdigit pause between signals. Thus, as

well as rejecting signals too short to be considered valid,

the receiver will tolerate signal interruptions (drop out)

too short to be considered a valid pause. This facility,

together with the capability of selecting the steering time

constants externally, allows the designer to tailor

performance to meet a wide variety of system

requirements.

SteeringCircuit

Before registration of a decoded tone pair, the receiver

VOLT

AGE GAIN

Figure 1. Single Ended Input Configuration

Figure 2. Differential Input Configuration

5/00

215 Topaz Street, Milpitas, California 95035

Tel: (408) 263-3214

Fax: (408) 263-7846

www.calmicro.com

1...4 5 678 9 10...13

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与CM8888-2相关器件

型号	品牌	描述	获取价格	数据表
CM8888-2CI	CALMIRCO	DTMF Signaling Circuit, CDIP20, CERAMIC, DIP-20	获取价格
CM8888-2DI	CALMIRCO	DTMF Signaling Circuit, CDIP20, CERDIP-20	获取价格
CM8888-2EI	CALMIRCO	DTMF Signaling Circuit, PQCC28, PLASTIC, LCC-28	获取价格
CM8888-2FI	ETC	Telecommunication IC	获取价格
CM8888-2LI	CALMIRCO	DTMF Signaling Circuit, PQCC28, PLASTIC, LCC-28	获取价格
CM8888-2PI	ETC	Telecommunication IC	获取价格
CM8888-2SI	CALMIRCO	DTMF Signaling Circuit, CMOS, PDSO20, SOIC-20	获取价格
CM8888-3C	CALMIRCO	DTMF Signaling Circuit, CDIP20, CERAMIC, DIP-20	获取价格
CM8888-3F	CALMIRCO	DTMF Signaling Circuit, PDSO20, EIAJ, SSOP-20	获取价格
CM8888-3P	CALMIRCO	DTMF Signaling Circuit, PDIP20, PLASTIC, DIP-20	获取价格

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