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CM8888-2

更新时间： 2024-01-31 19:07:51
品牌 Logo 应用领域
CALMIRCO /
页数 文件大小 规格书
13页 322K
描述
CMOS INTEGRATED DTMF TRANCEIVER

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中文翻译

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CM8888-2 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP,针数：20
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.82Is Samacsys：N
JESD-30 代码：R-PDSO-G20长度：12.905 mm
功能数量：1端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
认证状态：Not Qualified座面最大高度：2.85 mm
最大压摆率：10 mA标称供电电压：5 V
表面贴装：YES技术：CMOS
电信集成电路类型：DTMF SIGNALING CIRCUIT温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL宽度：7.635 mm
Base Number Matches：1

CM8888-2 数据手册

 浏览型号CM8888-2的Datasheet PDF文件第7页浏览型号CM8888-2的Datasheet PDF文件第8页浏览型号CM8888-2的Datasheet PDF文件第9页浏览型号CM8888-2的Datasheet PDF文件第10页浏览型号CM8888-2的Datasheet PDF文件第11页浏览型号CM8888-2的Datasheet PDF文件第12页 
CALIFORNIA MICRO DEVICES  
CM8888/8888-2  
Table 7. Status Register Description  
Bit  
Name  
Status Flag Set  
Status Flag Cleared  
bo  
IRQ  
Interrupt has occured. Bit one  
(b1) and/or bit two (b2) is set.  
Interrupt is inactive. Cleared after  
Status Register is read.  
b1  
Transmit Data Register  
Pause duration has terminated  
and transmitter is ready for  
new data.  
Cleared after Status Register is read  
or when in Non-Burst Mode.  
b2  
b3  
Receive Data Register Full  
Delayed Steering  
Valid data is in the Receive  
Data Register.  
Cleared after Status Register is  
read.  
Set upon the valid detection of  
the absence of a DTMF signal.  
Cleared upon the detection of a  
valid DTMF signal.  
Pin Function Table  
Name  
Description  
Name  
Description  
N+  
Non-inverting op-amp input.  
IRQ/CP Interupt request to microprocessor  
(open-drain output). Also, when  
Call Progress (CP) Mode has been  
selected and Interrupt enabled the  
IRQ/CP pin will output a rectangular  
wave signal representative of the  
input siganl applied at the input op-  
amp. The input signal must be  
IN-  
GS  
Inverting op-amp input  
Gain Select. Gives access to output of  
front end differential amplifier for  
connection of feedback resistor.  
VREF  
References voltage output. Nominally  
VDD /2 is used to bais inputs at inputs at  
mid-rail (see application circuit).  
within the bandwidth limits of the  
Call Progress filter. See Filter 6.  
DO-D3 Microprocessor data bus. TTL  
compatible.  
VSS  
Negative power supply input.  
OSC1 DTMF clock/oscillator input.  
ESt  
Early Spring output. Presents a  
logic high once the digital algorithm  
has detected a valid tone pair (signal  
condition). Any momentary loss of signal  
condition will cause EST to  
OSC2 Clock output. A 3.5795 MHz crystal  
connected between OSC1 AND OSC2  
completes the internal oscillator circuit.  
return to a logic low.  
TONE Dual tone Multi-Frequency (DTMF)  
output.  
StGT  
Steering input/Guard Time output  
(bidierectional). A voltage greater  
than VTS, detected at St causes the  
device to register the detected tone  
pair and update the output latch. A  
voltage less than VTS, frees the device  
to accept a new tone pair. The GT output  
acts to reset the external steering time-  
constant; its state is a function of ESt and  
the voltage on St.  
WR  
Write input. A low on this pin when  
CS is low enables data transfer from  
the microprocessor. TTL compatible.  
CS  
Chip Select. TTl input. (CS =0 to  
select the chip).  
RSO  
RD  
Register select input. See register  
decode table. TTL compatible.  
VDD  
Positive power supply input.  
Read input. A low on this pin when  
CS is low enables data transfer to the  
microprocessor. TTL compatible.  
© 2000 California Micro Devices Corp. All rights reserved.  
5/00  
215 Topaz Street, Milpitas, California 95035  
Tel: (408) 263-3214  
Fax: (408) 263-7846  
www.calmicro.com  
13  
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