Datasheet > CLC949AJQ

CLC949AJQ

更新时间： 2024-02-24 00:57:54

品牌	Logo	应用领域
美国国家半导体 - NSC		/
页数	文件大小	规格书
12页	740K
描述
Very Low-Power, 12-Bit, 20MSPS Monolithic A/D Convertter

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中文翻译

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技术参数
数据手册

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CLC949AJQ 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	PLASTIC, LCC-44	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.89	最大模拟输入电压：	2 V
最小模拟输入电压：	-2 V	转换器类型：	ADC, PROPRIETARY METHOD
JESD-30 代码：	S-PQCC-J44	JESD-609代码：	e0
最大线性误差 (EL)：	0.0854%	模拟输入通道数量：	1
位数：	12	功能数量：	1
端子数量：	44	最高工作温度：	85 °C
最低工作温度：	-40 °C	输出位码：	BINARY
输出格式：	PARALLEL, WORD	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装等效代码：	LDCC44,.7SQ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	5 V
认证状态：	Not Qualified	采样速率：	20 MHz
采样并保持/跟踪并保持：	SAMPLE	子类别：	Analog to Digital Converters
最大压摆率：	60 mA	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED

CLC949AJQ 数据手册

August 1996

Comlinear CLC949

Very Low-Power, 12-Bit,

20MSPS Monolithic A/D Convertter

General Description

Features

The Comlinear CLC949 is a 12-bit analog-to-digital converter sub-

system including 12-bit quantizer, sample-and-hold amplifier, and

internal reference. The CLC949 has been optimized for low power

operation with high dynamic range. The CLC949 has a unique

feature which allows the user to adjust internal bias levels in the

converter which results in a trade-off between power dissipation

and maximum conversion rate. With bias set for 220mW power

dissipation the converter operates at 20MSPS. Under these

conditions, dynamic performance with a 9.9MHz analog input is

typically 68dB SNR and 72dBc SFDR. When bias is set for only

65mW power dissipation the converter maintains excellent perfor-

mance at 5MSPS. With a 2.4MHz analog input signal the SNR is

70dB and SFDR is 78dBc. This excellent dynamic performance in

the frequency domain without high power requirements make the

part a strong performer for communications and radar applications.

The low input noise of the CLC949, its 0.5LSB differential linearity

error specification, fast settling, and low power dissipation also

lead to excellent performance in imaging systems. All parts are

thoroughly tested to insure that guaranteed specifications are met.

■

Very low/programmable power

0.07W @ 5MSPS

0.22W @ 20MSPS

0.40W @ 30MSPS

■

Single supply operation (+5V)

■

0.5 LSB differential linearity error

Wide dynamic range

■

72dBc spurious-free dynamic range

68dB signal-to-noise ratio

No missing codes

■

Applications

■

CCD imaging

■

IR imaging

■

FLIR processing

■

Medical imaging

■

High definition video

■

Instrumentation

■

Radar processing

Digital communications

The CLC949 incorporates an input sample-and-hold amplifier

followed by a quantizer which uses a pipelined architecture to min-

imize comparator count and the associated power dissipation

penalty. An on-board voltage reference is provided. Analog input

signals, conversion clock, and a single supply are all that are

required for CLC949 operation.

■

The CLC949 exhibits very stable performance over the commercial

and industrial temperature ranges. Most parameters shift very

little as the ambient temperature changes from -40°C to 85°C. An

exception to this rule is the dynamic performance of the converter.

As the temperature is increased, the distortion increases,

especially at higher input frequencies. This can be seen in the plot

on page 3. For input frequencies below 7MHz, there is relatively

little variation in distortion as the temperature is changed, but at

higher input frequencies, it is apparent that the performance

degrades as the temperature is increased.

SFDR (dBc)

Note that the reason for this degradation is the reduced ability of

the CLC949 to handle high slew rates at high temperatures. In

applications such as CCD imaging systems, where the slew rate at

the A/D sampling instant is very low, this degradation will not be

nearly so pronounced.

For applications requiring high temperature operation and very low

distortion with high frequency input signals, use of an external

sample-and-hold amplifier may enhance performance by reducing

the slew rates that the CLC949 sees during its sampling period (just

after the falling edge of CLK).

Power Dissipation vs. Conversion Rate

200

150

100

The CLC949 is fabricated in a 0.9µm CMOS technology. The

CLC949ACQ is specified over the commercial temperature range

of 0°C to +70°C and the CLC949AJQ is specified over the indus-

trial range of -40°C to +85°C. Both are packaged in a 44-pin

Plastic Leaded Chip Carrier (PLCC)

Sample Rate (MSPS)

Printed in the U.S.A.

http://www.national.com

12 3 4 5 6 7...12

中文翻译

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与CLC949AJQ相关器件

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CLC952	NSC	获取价格	CLC949ACQ
CLC952ACMSA	NSC	获取价格	CLC949ACQ
CLC952AJMSA	NSC	获取价格	CLC949ACQ
CLC952BAJMSA	ETC	获取价格	Analog-to-Digital Converter， 12-Bit
CLC952BAJMSA-TR13	TI	获取价格	1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28, PLASTIC, SSOP-28
CLC952BAJMSA-TR9	TI	获取价格	1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28, PLASTIC, SSOP-28
CLC952PCASM	NSC	获取价格	CLC949ACQ
CLC9-65608L-45:D	TEMIC	获取价格	Standard SRAM, 128KX8, 45ns, CMOS, CDIP32,
CLC9-65608L-45SHXXX	TEMIC	获取价格	Standard SRAM, 128KX8, 45ns, CMOS, CDIP32,
CLC9-65608L-45SHXXX:D	TEMIC	获取价格	Standard SRAM, 128KX8, 45ns, CMOS, CDIP32,

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