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CLC533A8L-2A

更新时间： 2024-01-02 15:26:26
品牌 Logo 应用领域
美国国家半导体 - NSC 复用器
页数 文件大小 规格书
9页 1309K
描述
High-Speed 4:1 Analog Multiplexer

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CLC533A8L-2A 技术参数

生命周期：Obsolete包装说明：QCCN,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.77模拟集成电路 - 其他类型：SINGLE-ENDED MULTIPLEXER
JESD-30 代码：S-CQCC-N20标称负供电电压 (Vsup)：-5.2 V
信道数量：4功能数量：1
端子数量：20最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：QCCN封装形状：SQUARE
封装形式：CHIP CARRIER认证状态：Not Qualified
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：BIPOLAR温度等级：MILITARY
端子形式：NO LEAD端子位置：QUAD
Base Number Matches：1

CLC533A8L-2A 数据手册

 浏览型号CLC533A8L-2A的Datasheet PDF文件第2页浏览型号CLC533A8L-2A的Datasheet PDF文件第3页浏览型号CLC533A8L-2A的Datasheet PDF文件第4页浏览型号CLC533A8L-2A的Datasheet PDF文件第6页浏览型号CLC533A8L-2A的Datasheet PDF文件第7页浏览型号CLC533A8L-2A的Datasheet PDF文件第8页 
Recommended Operating Conditions  
Absolute Maximum Ratings3  
positive supply voltage (+V )  
+5.0V  
-5.2V  
10mV  
positive supply voltage (+V )  
-0.5V to +7.0V  
+0.5V to -7.0V  
200mV  
cc  
cc  
negative supply voltage (-V )  
negative supply voltage (-V )  
ee  
ee  
differential voltage between any two GND’s  
analog input voltage range  
differential voltage between any two GND’s  
analog input voltage range  
digital input voltage range  
output short circuit duration (shorted to GND)  
junction temperature  
±2V  
0V to +5.0V  
0V to -2.0V  
-V to +V  
-V to +V  
ee  
ee  
cc  
cc  
A input voltage range (TTL mode)  
X
A input voltage range (ECL mode)  
Infinite  
+150°C  
X
C
range 5pF to 100pF  
COMP  
operating temperature range  
CLC533AJP/AJE/AIB  
storage temperature range  
lead solder duration (+300°C)  
ESD rating (human body model)  
thermal data  
16-pin plastic  
16-pin Cerdip  
16-pin SOIC  
20-terminal LCC  
16-pin side brazed 20  
θ (°C/W)  
θ (°C/W)  
jc  
ja  
-40°C to +85°C  
-65°C to +150°C  
10 sec  
50  
20  
60  
20  
60  
65  
75  
35  
50  
<500V  
Note 1: Test levels are as follows:  
cuit may be impaired. Functional operability under any of these  
conditions is not necessarily implied. Exposure to maximum rat-  
ings for extended periods may affect device reliability.  
*
AJ : 100% tested at +25°C.  
Note 2: Settling time measured from the 50% analog output  
transition.  
Package Thermal Resistance  
Note 3: Absolute maximum ratings are limiting values, to be  
applied individually, and beyond which the serviceability of the cir-  
Package  
θJC  
θJA  
AJP  
AJE  
CERDIP  
45°C/W  
35°C/W  
25°C/W  
95°C/W  
100°C/W  
65°C/W  
Reliability Information  
Transistor count  
144  
System Timing Diagram  
Switching Transient Timing Diagram  
APPLICATIONS INFORMATION  
Operation  
open, then the A and A select inputs will respond to  
0 1  
The CLC533 is a 4:1 analog multiplexer designed with a  
closed loop architecture to provide very low harmonic  
distortion and superior channel to channel isolation. This  
low distortion, coupled with very fast switching  
speed make the CLC533 an ideal multiplexer for data  
conversion applications. User selectable ECL or TTL  
select logic adds to the versatility of this device. External  
frequency response compensation allows the  
performance of the CLC533 to be optimized for each  
application.  
ECL 10K switching levels (Figure 1). For TTL or CMOS  
levels, D should be tied to V (Figure 2). There is an  
REF  
cc  
internal series resistor which makes it possible to  
connect D directly to the power supply. Select pins  
REF  
according to the truth table shown on the front page. A  
more positive voltage is considered to be a logic ‘1’.  
Therefore with no connection to A or A the internal pull-  
0
1
up resistors will select the D input to be passed through  
to the output.  
Compensation  
Digital Interface and Channel Select  
The CLC533 is externally compensated, allowing  
the user to select the bandwidth that best suits  
the application. Decreasing bandwidth has two  
advantages: lower noise and lower switching tran-  
sients. In a sampled system, noise at frequencies  
The CLC533 has two channel select pins which can be  
used to select any one of the four inputs. These  
digital inputs can be configured to meet TTL, ECL or  
CMOS logic levels with the D  
pin. If D  
is left  
REF  
REF  
5
http://www.national.com  
123456789

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