CDP1854A, CDP1854AC
SERIAL DATA IN (SDl):
Functional Definitions for CDP1854A
Terminals Mode 1 CDP1800-Series
Microprocessor Compatible
Serial data received on this input line enters the Receiver
Shift Register at a point determined by the character length.
A high-level input voltage must be present when data is not
being received.
SIGNAL: FUNCTION
CLEAR (CLEAR):
V
:
DD
A low-level voltage at this input resets the Interrupt Flip-
Flop, Receiver Holding Register, Control Register, and
Status Register, and sets SERIAL DATA OUT (SDO) high.
Positive supply voltage.
MODE SELECT (MODE):
A high-level voltage at this input selects CDP1800-series
microprocessor Mode operation.
TRANSMlTTER HOLDING REGISTER EMPTY (THRE):
A low-level voltage at this output indicates that the
Transmitter Holding Register has transferred its contents to
the Transmitter Shift Register and may be reloaded with a
new character.
V
:
SS
Ground
CHIP SELECT 2 (CS2):
CHIP SELECT 1 (CS1):
A low-level voltage at this input together with CS1 and CS3
selects the CDP1854A UART.
A high-level voltage at this input together with CS2 and CS3
selects the UART.
RECEIVER BUS (R BUS 7 - R BUS 0):
REQUEST TO SEND (RTS):
Receiver parallel data outputs (may be externally connected
to corresponding transmitter bus terminals).
This output signal tells the peripheraI to get ready to receive
data. CLEAR TO SEND (CTS) is the response from the
peripheral. RTS is set to a low-level voltage when data is
latched in the Transmitter Holding Register or TR is set high,
and is reset high when both the Transmitter Holding Register
and Transmitter Shift Register are empty and TR is low.
INTERRUPT (INT):
A low-level voltage at this output indicates the presence of
one or more of the interrupt conditions listed in Table 1.
FRAMlNG ERROR (FE):
SERAL DATA OUTPUT (SDO):
A high-level voltage at this output indicates that the received
character has no valid stop bit, i.e., the bit following the parity
bit (if programmed) is not a high-level voltage. This output is
updated each time a character is transferred to the Receiver
Holding Register.
The contents of the Transmitter Shift Register [start bit, data
bits, parity bit, and stop bit(s)] are serially shifted out on this
output. When no character is being transmitted, a high level
is maintained. Start of transmission is defined as the
transition of the start bit from a high-level to a low-level
output voltage.
PARITY ERROR or OVERRUN ERROR (PE/OE):
A high-level voltage at this output indicates that either the PE
or OE bit in the Status Register has been set (see Status
Register Bit Assignment, Table 2).
TRANSMlTTER BUS (T BUS 0 - T BUS 7):
Transmitter parallel data input. These may be externally
connected to corresponding Receiver bus terminals.
REGISTER SELECT (RSEL):
RD/WR:
This input is used to choose either the Control/Status
Registers (high input) or the transmitter/receiver data
registers (low input) according to the truth table in Table 3.
A low-level voltage at this input gates data from the transmitter
bus to the Transmitter Holding Register or the Control Regis-
ter as chosen by register select. A high-level voltage gates
data from the Receiver Holding Register or the Status Regis-
ter, as chosen by register select, to the receiver bus.
RECEIVER CLOCK (RCLOCK):
Clock input with a frequency 16 times the desired receiver
shift rate.
CHIP SELECT 3 (CS3):
TPB:
With high-level voltage at this input together with CS1 and
CS2 selects the UART.
A positive input pulse used as a data load or reset strobe.
PERIPHERAL STATUS INTERRUPT (PSI):
DATA AVAILABLE (DA):
A high-to-low transition on this input line sets a bit in the
Status Register and causes an INTERRUPT (INT = low).
A low-level voltage at this output indicates that an entire
character has been received and transferred to the Receiver
Holding Register.
EXTERNAL STATUS (ES):
A low-level voltage at this input sets a bit in the Status
Register.
5-47
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