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CDP1854ACE PDF预览

CDP1854ACE

更新时间: 2024-02-26 07:37:12
品牌 Logo 应用领域
英特矽尔 - INTERSIL /
页数 文件大小 规格书
21页 97K
描述
Programmable Universal Asynchronous Receiver/Transmitter (UART)

CDP1854ACE 技术参数

生命周期:Obsolete包装说明:,
Reach Compliance Code:unknown风险等级:5.84
Base Number Matches:1

CDP1854ACE 数据手册

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CDP1854A,  
CDP1854AC  
Programmable Universal Asynchronous  
Receiver/Transmitter (UART)  
March 1997  
Features  
Description  
• Two Operating Modes  
The CDP1854A and CDP1854AC are silicon-gate CMOS  
Universal Asynchronous Receiver/Transmitter (UART) cir-  
cuits. They are designed to provide the necessary formatting  
and control for interfacing between serial and parallel data.  
For example, these UARTs can be used to interface between  
a peripheral or terminal with serial I/O ports and the 8-bit  
CDP1800-series microprocessor parallel data bus system.  
The CDP1854A is capable of full duplex operation, i.e.,  
simultaneous conversion of serial input data to parallel out-  
put data and parallel input data to serial output data.  
- Mode 0 - Functionally Compatible with Industry  
Types Such as the TR1602A and CDP6402  
- Mode 1 - Interfaces Directly with CDP1800-Series  
Microprocessors without Additional Components  
• Full or Half Duplex Operation  
• Parity, Framing and Overrun Error Detection  
• Baud Rate  
- DC to 200K Bits/s at V . . . . . . . . . . . . . . . . . . . . 5V  
DD  
- DC to 400K Bits/s at V . . . . . . . . . . . . . . . . . . . .10V  
DD  
The CDP1854A UART can be programmed to operate in one  
of two modes by using the mode control input. When the  
input is high (MODE = 1), the CDP1854A is directly compati-  
ble with the CDP1800-series microprocessor system without  
additional interface circuitry. When the mode input is low  
(MODE = 0), the device is functionally compatible with indus-  
try standard UART’s such as the TR1602A and CDP6402. It  
is also pin compatible with these types, except that pin 2 is  
used for the mode control input.  
• Fully Programmable with Externally Selectable Word  
Length (5-8 Bits), Parity Inhibit, Even/Odd Parity, and  
1, 1-1/2, or 2 Stop Bits  
• False Start Bit Detection  
Ordering Information  
The CDP1854A and the CDP1854AC are functionally identi-  
cal. The CDP1854A has a recommended operating voltage  
range of 4V to 10.5V, and the CDP1854AC has a recom-  
mended operating voltage range of 4V to 6.5V.  
TEMP.  
RANGE  
o
5V/200K  
BAUD  
10V/400K  
BAUD  
PKG.  
NO.  
PACKAGE  
PDIP  
o
-40 C to +85 C CDP1854ACE  
CDP1854AE  
E40.6  
E40.6  
N44.65  
D40.6  
D40.6  
Burn-In  
PLCC  
CDP1854ACEX CDP1854AEX  
o
o
-40 C to +85 C CDP1854ACQ  
CDP1854AQ  
CDP1854AD  
-
o
o
SBDIP  
-40 C to +85 C CDP1854ACD  
CDP1854ACDX  
Burn-In  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 1193.2  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999  
5-42  

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