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CDC7005

更新时间： 2024-02-18 12:37:01
品牌 Logo 应用领域
德州仪器 - TI 时钟
页数 文件大小 规格书
29页 406K
描述
3.3-V HIGH PERFORMANCE CLOCK SYNTHESIZER AND JITTER CLEANER

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中文翻译

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CDC7005 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：BGA
包装说明：BGA-64针数：64
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：5.3
Is Samacsys：N其他特性：INTEGRATED LOW-NOISE OP AMP
系列：7005输入调节：DIFFERENTIAL
JESD-30 代码：S-PBGA-B64JESD-609代码：e1
长度：8 mm逻辑集成电路类型：PLL BASED CLOCK DRIVER
最大I（ol）：0.006 A湿度敏感等级：3
功能数量：1反相输出次数：
端子数量：64实输出次数：5
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LFBGA封装形状：SQUARE
封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH包装方法：TR
峰值回流温度（摄氏度）：260最大电源电流（ICC）：265 mA
传播延迟（tpd）：0.95 ns认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.06 ns座面最大高度：1.4 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：0.8 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：8 mm最小 fmax：800 MHz
Base Number Matches：1

CDC7005 数据手册

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SCAS685E − DECEMBER 2002 − REVISED NOVEMBER 2004  
TERMINAL ASSIGNMENTS  
(TOP VIEW)  
D
D
D
High Performance 1:5 PLL Clock  
Synchronizer  
1
2
3
4
5
6
7
8
Two Clock Inputs: VCXO_IN Clock Is  
Synchronized to REF_IN Clock  
CTRL_  
CLK  
CTRL_  
DATA  
STATUS_  
CP_OUT OPA_IN OPA_IP OPA_OUT  
LOCK  
A
CTRL_LE  
REF_IN  
Synchronizes Frequencies up to 800 MHz  
(VCXO_IN)  
B
C
D
E
F
GND  
GND  
GND  
GND  
GND  
AV  
GND  
GND  
D
Supports Five Differential LVPECL Outputs  
STATUS_  
REF  
I_REF  
GND  
GND  
AV  
CC  
AV  
CC  
AV  
CC  
AV  
CC  
CC  
D
Each Output Frequency Is Selectable by x1,  
/2, /4, /8, /16  
STATUS_  
VCXO  
VCXO_IN  
GND  
GND  
GND  
GND  
V
CC  
D
D
D
All Outputs Are Synchronized  
Integrated Low-Noise OPA for External  
Low-Pass Filter  
VCXO_IN  
B
GND  
GND  
V
V
V
V
V
V
CC  
CC  
CC  
CC  
CC  
CC  
Efficient Jitter Screening From Low PLL  
Loop Bandwidth  
Y0  
GND  
GND  
GND  
GND  
Y4B  
Y4  
V
CC  
Y0B  
NPD  
D
Low-Phase Noise Characteristic  
G
H
V
V
V
V
V
CC  
CC  
CC  
CC  
V
CC  
CC  
D
Programmable Delay for Phase  
Adjustments  
Y1  
Y1B  
Y2  
Y2B  
Y3  
Y3B  
NRESET  
D
D
D
Predivider Loop BW Adjustment  
SPI Controllable Division Setting  
Power-Up Control Forces LVPECL Outputs  
to 3-State at VCC <1.5 V  
D
3.3-V Power Supply  
D
Available in a 64-Pin BGA Package  
0,8-mm Pitch in Both Lead-Free ZVA and  
Leaded GVA Packages  
D
Industrial Temperature Range –40°C to  
85°C  
description  
The CDC7005 is a high-performance, low-phase noise, and low-skew clock synthesizer and jitter cleaner that  
synchronizes the voltage controlled crystal oscillator (VCXO) frequency to the reference clock. The  
programmable predividers M and N give a high flexibility to the frequency ratio of the reference clock to VCXO:  
VCXO_IN/REF_IN = (NxP)/M. The VCXO_IN clock operates up to 800 MHz. Through the selection of external  
VCXO and loop filter components, the PLL loop bandwidth and damping factor can be adjusted to meet different  
system requirements. Each of the five differential LVPECL outputs are programmable by the serial peripheral  
interface (SPI). The SPI allows individual control of frequency and enable/disable state of each output. The  
device operates in 3.3-V environment. The built-in latches ensure that all outputs are synchronized.  
The CDC7005 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2004, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...29

中文翻译

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