CDC111
1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER
SCAS321G – SEPTEMBER 1993 – REVISED AUGUST 1999
FN PACKAGE
(TOP VIEW)
Low-Output Skew for Clock-Distribution
Applications
Differential Low-Voltage Pseudo-ECL
(LVPECL)-Compatible Inputs and Outputs
Distributes Differential Clock Inputs to Nine
Differential Clock Outputs
4
3
2 1 28 27 26
5
25
24
23
22
21
20
19
Y8
Y8
Y7
Y0
Y0
Y1
Output Reference Voltage, V
, Allows
6
REF
Distribution From a Single-Ended Clock
Input
7
8
V
V
CC0
Y7
Y6
Y6
CC0
9
Single-Ended LVPECL-Compatible Output
Enable
Y1
Y2
Y2
10
11
Packaged in Plastic Chip Carrier
1213 14 15 16 17 18
description
The differential LVPECL clock-driver circuit
distributes one pair of differential LVPECL clock
inputs (CLKIN, CLKIN) to nine pairs of differential
clock (Y, Y) outputs with minimum skew for clock
distribution. It is specifically designed for driving
50-Ω transmission lines.
NC – No internal connection
When the output-enable (OE) is low, the nine differential outputs switch at the same frequency as the differential
clock inputs. When OE is high, the nine differential outputs are in static states (Y outputs are in the low state,
Y outputs are in the high state).
The V
output can be strapped to the CLKIN input for a single-ended CLKIN input.
REF
The CDC111 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUTS
CLKIN CLKIN
OE
H
L
Yn
L
Yn
H
X
L
X
H
L
L
H
H
L
L
H
L
L
V
V
L
REF
H
L
H
L
H
H
L
REF
L
V
V
L
L
REF
H
L
H
REF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
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