CD54HC4094, CD74HC4094,
CD74HCT4094
Data sheet acquired from Harris Semiconductor
SCHS211D
High-Speed CMOS Logic
8-Stage Shift and Store Bus Register, Three-State
November 1997 - Revised October 2003
Two serial outputs are available for cascading a number of
Features
• Buffered Inputs
these devices. Data is available at the QS serial output
1
terminal on positive clock edges to allow for high-speed
operation in cascaded system in which the clock rise time is
• Separate Serial Outputs Synchronous to Both
Positive and Negative Clock Edges For Cascading
[ /Title
(CD74H
C4094,
CD74H
CT4094
)
/Sub-
ject
(High
Speed
CMOS
Logic 8-
fast. The same serial information, available at the QS
2
terminal on the next negative clock edge, provides a means
for cascading these devices when the clock rise time is slow.
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Ordering Information
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
TEMP. RANGE
o
PART NUMBER
CD54HC4094F3A
CD74HC4094E
( C)
PACKAGE
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld SOP
• Significant Power Reduction Compared to LSTTL
Logic ICs
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
• HC Types
- 2V to 6V Operation
CD74HC4094M
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
at V
= 5V
CD74HC4094MT
CD74HC4094M96
CD74HC4094NSR
CD74HC4094PW
CD74HC4094PWR
CD74HC4094PWT
CD74HCT4094E
CD74HCT4094M
CD74HCT4094MT
CD74HCT4094M96
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
16 Ld TSSOP
16 Ld TSSOP
16 Ld TSSOP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
Description
The ’HC4094 and CD74HCT4094 are 8-stage serial shift
registers having a storage latch associated with each stage
for strobing data from the serial input to parallel buffered
three-state outputs. The parallel outputs may be connected
directly to common bus lines. Data is shifted on positive
clock transitions. The data in each shift register stage is
transferred to the storage register when the Strobe input is
high. Data in the storage register appears at the outputs
whenever the Output-Enable signal is high.
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
Pinout
CD54HC4094 (CERDIP)
CD74HC4094 (PDIP, SOIC, SOP, TSSOP)
CD74HCT4094 (PDIP, SOIC)
TOP VIEW
STROBE
DATA
CP
1
2
3
4
5
6
7
8
16 V
CC
15 OE
14 Q
13 Q
12 Q
11 Q
4
5
6
7
Q
Q
Q
Q
0
1
2
3
10 QS
2
9
QS
GND
1
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1