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CD74HCT4094M

更新时间： 2024-01-31 00:00:14
品牌 Logo 应用领域
哈里斯 - HARRIS 存储光电二极管
页数 文件大小 规格书
8页 69K
描述
High Speed CMOS Logic 8-Stage Shift and Store Bus Register, Three-State

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CD74HCT4094M 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：SOP, SOP16,.25Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.67
其他特性：PARALLEL OUTPUT IS LATCHED; UNLATCHED SERIAL SHIFT RIGHT OUTPUT计数方向：RIGHT
系列：HCTJESD-30 代码：R-PDSO-G16
JESD-609代码：e0逻辑集成电路类型：SERIAL IN PARALLEL OUT
最大频率@ Nom-Sup：20000000 Hz位数：8
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE电源：5 V
传播延迟（tpd）：43 ns认证状态：Not Qualified
子类别：Shift Registers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL触发器类型：POSITIVE EDGE
最小 fmax：60 MHzBase Number Matches：1

CD74HCT4094M 数据手册

 浏览型号CD74HCT4094M的Datasheet PDF文件第2页浏览型号CD74HCT4094M的Datasheet PDF文件第3页浏览型号CD74HCT4094M的Datasheet PDF文件第4页浏览型号CD74HCT4094M的Datasheet PDF文件第5页浏览型号CD74HCT4094M的Datasheet PDF文件第6页浏览型号CD74HCT4094M的Datasheet PDF文件第7页 
CD74HC4094,  
CD74HCT4094  
Semiconductor  
High Speed CMOS Logic  
November 1997  
8-Stage Shift and Store Bus Register, Three-State  
Features  
Description  
• Buffered Inputs  
The Harris CD74HC4094 and CD74HCT4094 are 8-stage  
serial shift registers having a storage latch associated with  
• Separate Serial Outputs Synchronous to Both  
Positive and Negative Clock Edges For Cascading  
[ /Title  
(CD74H  
C4094,  
CD74H  
CT4094  
)
each stage for strobing data from the serial input to parallel  
buffered three-state outputs. The parallel outputs may be  
connected directly to common bus lines. Data is shifted on  
positive clock transitions. The data in each shift register  
stage is transferred to the storage register when the Strobe  
input is high. Data in the storage register appears at the  
outputs whenever the Output-Enable signal is high.  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
/Sub-  
ject  
Two serial outputs are available for cascading a number of  
these devices. Data is available at the QS serial output  
1
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
terminal on positive clock edges to allow for high-speed  
operation in cascaded system in which the clock rise time is  
(High  
Speed  
CMOS  
Logic 8-  
fast. The same serial information, available at the QS  
terminal on the next negative clock edge, provides a means  
for cascading these devices when the clock rise time is slow.  
2
• HC Types  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
CC  
Ordering Information  
• HCT Types  
PKG.  
- 4.5V to 5.5V Operation  
o
PART NUMBER TEMP. RANGE ( C) PACKAGE  
NO.  
E16.3  
E16.3  
- Direct LSTTL Input Logic Compatibility,  
CD74HC4094E  
CD74HCT4094E  
CD74HC4094M  
CD74HCT4094M  
NOTES:  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
16 Ld PDIP  
16 Ld PDIP  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
l
OL OH  
16 Ld SOIC M16.15  
16 Ld SOIC M16.15  
Pinout  
CD74HC4094, CD74HCT4094  
(PDIP, SOIC)  
1. When ordering, use the entire part number. Add the suffix 96 to  
obtain the variant in the tape and reel.  
TOP VIEW  
2. Wafer or die for this part number is available which meets all elec-  
trical specifications. Please contact your local sales office or  
Harris customer service for ordering information.  
STROBE  
DATA  
CP  
1
2
3
4
5
6
7
8
16 V  
CC  
15 OE  
14 Q  
13 Q  
12 Q  
11 Q  
4
5
6
7
Q
Q
Q
Q
0
1
2
3
10 QS  
2
9
QS  
GND  
1
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
File Number 1779.1  
Copyright © Harris Corporation 1997  
1
12345678

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