Datasheet > CD74HCT4094MTG4

CD74HCT4094MTG4

更新时间： 2024-02-04 14:03:23

品牌	Logo	应用领域
德州仪器 - TI		存储
页数	文件大小	规格书
18页	513K
描述
High-Speed CMOS Logic 8-Stage Shift and Store Bus Register, Three-State

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CD74HCT4094MTG4 数据手册

CD54HC4094, CD74HC4094,

CD74HCT4094

Data sheet acquired from Harris Semiconductor

SCHS211D

High-Speed CMOS Logic

8-Stage Shift and Store Bus Register, Three-State

November 1997 - Revised October 2003

Two serial outputs are available for cascading a number of

Features

• Buffered Inputs

these devices. Data is available at the QS serial output

terminal on positive clock edges to allow for high-speed

operation in cascaded system in which the clock rise time is

• Separate Serial Outputs Synchronous to Both

Positive and Negative Clock Edges For Cascading

[ /Title

(CD74H

C4094,

CD74H

CT4094

)

/Sub-

ject

(High

Speed

CMOS

Logic 8-

fast. The same serial information, available at the QS

terminal on the next negative clock edge, provides a means

for cascading these devices when the clock rise time is slow.

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

Ordering Information

• Wide Operating Temperature Range . . . -55 C to 125 C

• Balanced Propagation Delay and Transition Times

TEMP. RANGE

PART NUMBER

CD54HC4094F3A

CD74HC4094E

( C)

PACKAGE

16 Ld CERDIP

16 Ld PDIP

16 Ld SOIC

16 Ld SOP

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

-55 to 125

• HC Types

- 2V to 6V Operation

CD74HC4094M

- High Noise Immunity: N = 30%, N = 30% of V

IL IH CC

at V

= 5V

CD74HC4094MT

CD74HC4094M96

CD74HC4094NSR

CD74HC4094PW

CD74HC4094PWR

CD74HC4094PWT

CD74HCT4094E

CD74HCT4094M

CD74HCT4094MT

CD74HCT4094M96

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V = 0.8V (Max), V = 2V (Min)

IL IH

16 Ld TSSOP

16 Ld PDIP

16 Ld SOIC

- CMOS Input Compatibility, I ≤ 1µA at V , V

OL OH

Description

The ’HC4094 and CD74HCT4094 are 8-stage serial shift

registers having a storage latch associated with each stage

for strobing data from the serial input to parallel buffered

three-state outputs. The parallel outputs may be connected

directly to common bus lines. Data is shifted on positive

clock transitions. The data in each shift register stage is

transferred to the storage register when the Strobe input is

high. Data in the storage register appears at the outputs

whenever the Output-Enable signal is high.

NOTE: When ordering, use the entire part number. The sufﬁxes 96

and R denote tape and reel. The sufﬁx T denotes a small-quantity

reel of 250.

Pinout

CD54HC4094 (CERDIP)

CD74HC4094 (PDIP, SOIC, SOP, TSSOP)

CD74HCT4094 (PDIP, SOIC)

TOP VIEW

STROBE

DATA

16 V

15 OE

14 Q

13 Q

12 Q

11 Q

10 QS

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

12 3 4 5 6 7...18

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与CD74HCT4094MTG4相关器件

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