CD74HCT297

更新时间： 2024-01-25 16:38:15

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
11页	99K
描述
High-Speed CMOS Logic Digital Phase-Locked-Loop

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CD74HCT297 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	SOP, SOP16,.25	Reach Compliance Code：	unknown
风险等级：	5.92	JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e0	端子数量：	16
最高工作温度：	125 °C	最低工作温度：	-55 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP16,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	电源：	5 V
子类别：	PLL or Frequency Synthesis Circuits	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	MILITARY	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL

CD74HCT297 数据手册

CD74HC297,

CD74HCT297

Data sheet acquired from Harris Semiconductor

SCHS177

High-Speed CMOS Logic

Digital Phase-Locked-Loop

November 1997

Features

Description

• Digital Design Avoids Analog Compensation Errors

• Easily Cascadable for Higher Order Loops

The Harris CD74HC297 and CD74HCT297 are high-speed

silicon gate CMOS devices that are pin-compatible with low

power Schottky TTL (LSTTL).

[ /Title

(CD74

HC297

CD74

HCT29

• Useful Frequency Range

These devices are designed to provide a simple, cost-effec-

tive solution to high-accuracy, digital, phase-locked-loop appli-

cations. They contain all the necessary circuits, with the

exception of the divide-by-N counter, to build first-order

phase-locked-loops.

- K-Clock . . . . . . . . . . . . . . . . . . . . . . . . . .DC to 55MHz (Typ)

- I/D-Clock . . . . . . . . . . . . . . . . . . . . DC to 35MHz (Typ)

• Dynamically Variable Bandwidth

• Very Narrow Bandwidth Attainable

• Power-On Reset

Both EXCLUSIVE-OR (XORPD) and edge-controlled phase

detectors (ECPD) are provided for maximum flexibility. The

input signals for the EXCLUSIVE-OR phase detector must

have a 50% duty factor to obtain the maximum lock-range.

/Sub-

ject

• Output Capability

- Standard. . . . . . . . . . . . . . . . . . . . XORPD

, ECPD

OUT

(High-

Speed

CMOS

Logic

Digi-

tal

Proper partitioning of the loop function, with many of the build-

ing blocks external to the package, makes it easy for the

designer to incorporate ripple cancellation (see Figure 2) or to

cascade to higher order phase-locked-loops.

- Bus Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/D

• Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

The length of the up/down K-counter is digitally programmable

according to the K-counter function table. With A, B, C and D

all LOW, the K-counter is disabled. With A HIGH and B, C and

D LOW, the K-counter is only three stages long, which widens

the bandwidth or capture range and shortens the lock time of

the loop. When A, B, C and D are all programmed HIGH, the

K-counter becomes seventeen stages long, which narrows

the bandwidth or capture range and lengthens the lock time.

Real-time control of loop bandwidth by manipulating the A to

D inputs can maximize the overall performance of the digital

phase-locked-loop.

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL

Logic ICs

Phase-

Locked

• CD74HC297 Types

- Operation Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 to 6V

- High Noise ImmunityN = 30%, N = 30% of V at 5V

IL IH CC

• CD74HCT297 Types

- Operation Voltage . . . . . . . . . . . . . . . . . . . . . . . . 4.5 to 5.5V

- Direct LSTTL Input Logic Compatibility

The CD74HC297 and CD74HCT297 can perform the classic

first order phase-locked-loop function without using analog

components. The accuracy of the digital phase-locked-loop

= 0.8V (Max), V = 2V (Min)

- CMOS Input Compatibility I ≤ 1µA at V , V

OL OH

(DPLL) is not affected by V

depends solely on accuracies of the K-clock and loop propa-

gation delays.

and temperature variations but

Ordering Information

PKG.

NO.

PART NUMBER TEMP. RANGE ( C) PACKAGE

CD74HC297E

CD74HCT297E

NOTES:

-55 to 125

16 Ld PDIP

E16.3

Pinout

CD74HC297, CD74HCT297 (PDIP)

TOP VIEW

1. When ordering, use the entire part number. Add the sufﬁx 96 to

obtain the variant in the tape and reel.

16 V

15 C

14 D

2. Wafer or die for this part number is available which meets all elec-

trical specifications. Please contact your local sales office or

Harris customer service for ordering information.

CTR

13 φA

I/D

12 ECPD

OUT

D/U

11 XORPD

OUT

10 φB

I/D

OUT

φA

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

File Number 1852.1

12 3 4 5 6 7...11

中文翻译

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与CD74HCT297相关器件

型号	品牌	获取价格	描述	数据表
CD74HCT297E	TI	获取价格	High-Speed CMOS Logic Digital Phase-Locked-Loop
CD74HCT297E	RENESAS	获取价格	IC,PHASE-LOCKED LOOP,HCT-CMOS,DIP,16PIN,PLASTIC
CD74HCT297EE4	TI	获取价格	High-Speed CMOS Logic Digital Phase-Locked Loop
CD74HCT297EN	ETC	获取价格	Analog IC
CD74HCT297F	ETC	获取价格	Analog IC
CD74HCT297H	RENESAS	获取价格	IC,PHASE-LOCKED LOOP,HCT-CMOS,DIE
CD74HCT297M	ETC	获取价格	Analog IC
CD74HCT299	TI	获取价格	High Speed CMOS Logic 8-Bit Universal Shift Register; Three-State
CD74HCT299E	TI	获取价格	High Speed CMOS Logic 8-Bit Universal Shift Register; Three-State
CD74HCT299EE4	TI	获取价格	High-Speed CMOS Logic 8-Bit Universal Shift Register; Three-State

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