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CD74HC4515ME4 PDF预览

CD74HC4515ME4

更新时间： 2024-09-14 23:04:27
品牌 Logo 应用领域
德州仪器 - TI 解码器驱动器解复用器锁存器逻辑集成电路光电二极管输入元件双倍数据速率
页数 文件大小 规格书
14页 230K
描述
HIGH-SPEED CMOS LOGIC 4-TO-16 LINE DECODER/DEMULTIPLEXER WITH INPUT LATCHES

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中文翻译

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CD74HC4515ME4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：GREEN, PLASTIC, SOIC-24针数：24
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.23
Is Samacsys：N其他特性：ADDRESS LATCHES
系列：HC/UH输入调节：LATCHED
JESD-30 代码：R-PDSO-G24JESD-609代码：e4
长度：15.4 mm负载电容（CL）：50 pF
逻辑集成电路类型：OTHER DECODER/DRIVER最大I（ol）：0.004 A
湿度敏感等级：1功能数量：1
端子数量：24最高工作温度：125 °C
最低工作温度：-55 °C输出极性：INVERTED
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP24,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE包装方法：TUBE
峰值回流温度（摄氏度）：260电源：2/6 V
Prop。Delay @ Nom-Sup：83 ns传播延迟（tpd）：415 ns
认证状态：Not Qualified座面最大高度：2.65 mm
子类别：Decoder/Drivers最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：4.5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.5 mmBase Number Matches：1

CD74HC4515ME4 数据手册

 浏览型号CD74HC4515ME4的Datasheet PDF文件第2页浏览型号CD74HC4515ME4的Datasheet PDF文件第3页浏览型号CD74HC4515ME4的Datasheet PDF文件第4页浏览型号CD74HC4515ME4的Datasheet PDF文件第5页浏览型号CD74HC4515ME4的Datasheet PDF文件第6页浏览型号CD74HC4515ME4的Datasheet PDF文件第7页 
CD54HC4514, CD74HC4514,  
CD74HC4515  
Data sheet acquired from Harris Semiconductor  
SCHS280C  
High-Speed CMOS Logic 4- to 16-Line  
November 1997 - Revised July 2003  
Decoder/Demultiplexer with Input Latches  
Features  
Description  
• Multifunction Capability  
The CD54HC4514, CD74HC4514, and CD74HC4515 are  
high-speed silicon gate devices consisting of a 4-bit strobed  
latch and a 4- to 16-line decoder. The selected output is  
enabled by a low on the enable input (E). A high on E inhibits  
selection of any output. Demultiplexing is accomplished by  
- Binary to 1-of-16 Decoder  
- 1-to-16 Line Demultiplexer  
• Fanout (Over Temperature Range)  
[ /Title  
(CD74  
HC451  
4,  
CD74  
HC451  
5)  
/Sub-  
ject  
(High  
Speed  
CMOS  
using the E input as the data input and the select inputs (A0-  
A3) as addresses. This E input also serves as a chip select  
when these devices are cascaded.  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
When Latch Enable (LE) is high the output follows changes  
in the inputs (see truth table). When LE is low the output is  
isolated from changes in the input and remains at the level  
(high for the 4514, low for the 4515) it had before the latches  
were enabled. These devices, enhanced versions of the  
equivalent CMOS types, can drive 10 LSTTL loads.  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
• HC Types  
- 2V to 6V Operation  
Ordering Information  
- High Noise Immunity: N = 30%, N = 30% of V  
IL  
IH  
CC  
at V  
= 5V  
CC  
o
PART NUMBER  
CD54HC4514F3A  
CD74HC4514E  
TEMP. RANGE ( C)  
-55 to 125  
PACKAGE  
24 Ld CERDIP  
24 Ld PDIP  
24 Ld PDIP  
24 Ld SOIC  
24 Ld SOIC  
24 Ld PDIP  
24 Ld PDIP  
24 Ld SOIC  
24 Ld SOIC  
Pinout  
-55 to 125  
CD54HC4514  
(CERDIP)  
CD74HC4514, CD74HC4515  
(PDIP, SOIC)  
CD74HC4514EN  
CD74HC4514M  
CD74HC4514M96  
CD74HC4515E  
-55 to 125  
-55 to 125  
TOP VIEW  
-55 to 125  
-55 to 125  
LE  
A0  
A1  
Y7  
Y6  
Y5  
Y4  
Y3  
Y1  
1
2
3
4
5
6
7
8
9
24  
V
CC  
23 E  
CD74HC4515EN  
CD74HC4515M  
CD74HC4515M96  
-55 to 125  
22 A3  
21 A2  
20 Y10  
19 Y11  
18 Y8  
-55 to 125  
-55 to 125  
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel.  
17 Y9  
16 Y14  
15 Y15  
14 Y12  
13 Y13  
Y2 10  
Y0 11  
GND 12  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
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 		IC,COUNTER,UP/DOWN,4-BIT BINARY,HC-CMOS,SOP,16PIN,PLASTIC

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