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CD74HC4520 PDF预览

CD74HC4520

更新时间: 2024-11-05 22:40:03
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德州仪器 - TI 计数器
页数 文件大小 规格书
8页 47K
描述
High Speed CMOS Logic Dual Synchronous Counters

CD74HC4520 数据手册

 浏览型号CD74HC4520的Datasheet PDF文件第2页浏览型号CD74HC4520的Datasheet PDF文件第3页浏览型号CD74HC4520的Datasheet PDF文件第4页浏览型号CD74HC4520的Datasheet PDF文件第5页浏览型号CD74HC4520的Datasheet PDF文件第6页浏览型号CD74HC4520的Datasheet PDF文件第7页 
CD74HC4518, CD74HC4520,  
CD74HCT4520  
Data sheet acquired from Harris Semiconductor  
SCHS216  
High Speed CMOS Logic  
Dual Synchronous Counters  
November 1997  
Features  
Description  
• Positive or Negative Edge Triggering  
• Synchronous Internal Carry Propagation  
• Fanout (Over Temperature Range)  
The Harris CD74HC4518 is a dual BCD up-counter. The  
Harris CD74HC4520 and CD74HCT4520 are dual binary  
up-counters. Each device consists of two independent  
internally synchronous 4-stage counters. The counter stages  
are D-type flip-flops having interchangeable CLOCK and  
[ /Title  
(CD74  
HC451  
8,  
CD74  
HC452  
0,  
CD74  
HCT45  
20)  
/Sub-  
ject  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
ENABLE lines for incrementing on either the positive-going  
or the negative-going transition of CLOCK. The counters are  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C cleared by high levels on the MASTER RESET lines. The  
counter can be cascaded in the ripple mode by connecting  
• Balanced Propagation Delay and Transition Times  
Q to the ENABLE input of the subsequent counter while the  
3
CLOCK input of the latter is held low.  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
Ordering Information  
• HC Types  
- 2V to 6V Operation  
PKG.  
o
PART NUMBER TEMP. RANGE ( C) PACKAGE  
NO.  
E16.3  
E16.3  
E16.3  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
CC  
CD74HC4518E  
CD74HC4520E  
CD74HCT4520E  
CD74HC4520M  
CD74HCT4520M  
NOTES:  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
16 Ld PDIP  
16 Ld PDIP  
16 Ld PDIP  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
16 Ld SOIC M16.15  
16 Ld SOIC M16.15  
- CMOS Input Compatibility, I 1µA at V , V  
OL OH  
l
1. When ordering, use the entire part number. Add the suffix 96 to  
obtain the variant in the tape and reel.  
2. Wafer or die for this part number is available which meets all elec-  
trical specifications. Please contact your local sales office or  
Harris customer service for ordering information.  
Pinout  
CD74HC4518  
CD74HC4520, CD74HCT4520  
(PDIP, SOIC)  
TOP VIEW  
1CP  
1E  
1
2
3
4
5
6
7
8
16 V  
CC  
15 2MR  
1Q  
1Q  
1Q  
1Q  
14 2Q  
13 2Q  
12 2Q  
11 2Q  
10 2E  
0
1
2
3
3
2
1
0
1MR  
GND  
9
2CP  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
File Number 1665.1  
Copyright © Harris Corporation 1997  
1

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高速 CMOS 逻辑双路二进制加法计数器 | D | 16 | -55 to 125