5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 解码器/驱动器> CD74HC4514M96
CD74HC4514M96 PDF预览

CD74HC4514M96

更新时间： 2024-11-23 23:04:27
品牌 Logo 应用领域
德州仪器 - TI 解码器驱动器解复用器锁存器逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
14页 230K
描述
HIGH-SPEED CMOS LOGIC 4-TO-16 LINE DECODER/DEMULTIPLEXER WITH INPUT LATCHES

阅读下载

中文翻译

获取价格

CD74HC4514M96 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：SOIC
包装说明：SOIC-24针数：24
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：0.79Samacsys Confidence：4
Samacsys Status：ReleasedSamacsys PartID：630719
Samacsys Pin Count：24Samacsys Part Category：Integrated Circuit
Samacsys Package Category：Small Outline PackagesSamacsys Footprint Name：DW (R-PDSO-G24)
Samacsys Released Date：2017-10-16 01:09:10Is Samacsys：N
其他特性：ADDRESS LATCHES系列：HC/UH
输入调节：LATCHEDJESD-30 代码：R-PDSO-G24
JESD-609代码：e4长度：15.4 mm
负载电容（CL）：50 pF逻辑集成电路类型：OTHER DECODER/DRIVER
最大I（ol）：0.0052 A湿度敏感等级：1
位数：16功能数量：1
端子数量：24最高工作温度：125 °C
最低工作温度：-55 °C输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP24,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE包装方法：TR
峰值回流温度（摄氏度）：260电源：2/6 V
最大电源电流（ICC）：0.08 mAProp。Delay @ Nom-Sup：23 ns
传播延迟（tpd）：415 ns认证状态：Not Qualified
座面最大高度：2.65 mm子类别：Decoder/Drivers
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：4.5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.5 mm
Base Number Matches：1

CD74HC4514M96 数据手册

 浏览型号CD74HC4514M96的Datasheet PDF文件第2页浏览型号CD74HC4514M96的Datasheet PDF文件第3页浏览型号CD74HC4514M96的Datasheet PDF文件第4页浏览型号CD74HC4514M96的Datasheet PDF文件第5页浏览型号CD74HC4514M96的Datasheet PDF文件第6页浏览型号CD74HC4514M96的Datasheet PDF文件第7页 
CD54HC4514, CD74HC4514,  
CD74HC4515  
Data sheet acquired from Harris Semiconductor  
SCHS280C  
High-Speed CMOS Logic 4- to 16-Line  
November 1997 - Revised July 2003  
Decoder/Demultiplexer with Input Latches  
Features  
Description  
• Multifunction Capability  
The CD54HC4514, CD74HC4514, and CD74HC4515 are  
high-speed silicon gate devices consisting of a 4-bit strobed  
latch and a 4- to 16-line decoder. The selected output is  
enabled by a low on the enable input (E). A high on E inhibits  
selection of any output. Demultiplexing is accomplished by  
- Binary to 1-of-16 Decoder  
- 1-to-16 Line Demultiplexer  
• Fanout (Over Temperature Range)  
[ /Title  
(CD74  
HC451  
4,  
CD74  
HC451  
5)  
/Sub-  
ject  
(High  
Speed  
CMOS  
using the E input as the data input and the select inputs (A0-  
A3) as addresses. This E input also serves as a chip select  
when these devices are cascaded.  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
When Latch Enable (LE) is high the output follows changes  
in the inputs (see truth table). When LE is low the output is  
isolated from changes in the input and remains at the level  
(high for the 4514, low for the 4515) it had before the latches  
were enabled. These devices, enhanced versions of the  
equivalent CMOS types, can drive 10 LSTTL loads.  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
• HC Types  
- 2V to 6V Operation  
Ordering Information  
- High Noise Immunity: N = 30%, N = 30% of V  
IL  
IH  
CC  
at V  
= 5V  
CC  
o
PART NUMBER  
CD54HC4514F3A  
CD74HC4514E  
TEMP. RANGE ( C)  
-55 to 125  
PACKAGE  
24 Ld CERDIP  
24 Ld PDIP  
24 Ld PDIP  
24 Ld SOIC  
24 Ld SOIC  
24 Ld PDIP  
24 Ld PDIP  
24 Ld SOIC  
24 Ld SOIC  
Pinout  
-55 to 125  
CD54HC4514  
(CERDIP)  
CD74HC4514, CD74HC4515  
(PDIP, SOIC)  
CD74HC4514EN  
CD74HC4514M  
CD74HC4514M96  
CD74HC4515E  
-55 to 125  
-55 to 125  
TOP VIEW  
-55 to 125  
-55 to 125  
LE  
A0  
A1  
Y7  
Y6  
Y5  
Y4  
Y3  
Y1  
1
2
3
4
5
6
7
8
9
24  
V
CC  
23 E  
CD74HC4515EN  
CD74HC4515M  
CD74HC4515M96  
-55 to 125  
22 A3  
21 A2  
20 Y10  
19 Y11  
18 Y8  
-55 to 125  
-55 to 125  
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel.  
17 Y9  
16 Y14  
15 Y15  
14 Y12  
13 Y13  
Y2 10  
Y0 11  
GND 12  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
1234567...14

中文翻译

下载PDF

CD74HC4514M96 替代型号

型号 品牌 替代类型 描述 数据表
CD74HC4514MG4 TI

完全替代

 High-Speed CMOS Logic 4- to 16-Line Decoder/Demultiplexer with Input Latches
CD74HC154M96 TI

完全替代

 High-Speed CMOS Logic 4- to 16-Line Decoder/Demultiplexer
CD74HC154M TI

完全替代

 High Speed CMOS Logic 4-to-16 Line Decoder/Demultiplexer

与CD74HC4514M96相关器件

型号 品牌 获取价格 描述 数据表
CD74HC4514M96E4 TI

获取价格

 		HIGH-SPEED CMOS LOGIC 4-TO-16 LINE DECODER/DEMULTIPLEXER WITH INPUT LATCHES
CD74HC4514M96G4 TI

获取价格

 		High-Speed CMOS Logic 4- to 16-Line Decoder/Demultiplexer with Input Latches
CD74HC4514ME4 TI

获取价格

 		HIGH-SPEED CMOS LOGIC 4-TO-16 LINE DECODER/DEMULTIPLEXER WITH INPUT LATCHES
CD74HC4514MG4 TI

获取价格

 		High-Speed CMOS Logic 4- to 16-Line Decoder/Demultiplexer with Input Latches
CD74HC4515 TI

获取价格

 		HIGH-SPEED CMOS LOGIC 4-TO-16 LINE DECODER/DEMULTIPLEXER WITH INPUT LATCHES
CD74HC4515E TI

获取价格

 		HIGH-SPEED CMOS LOGIC 4-TO-16 LINE DECODER/DEMULTIPLEXER WITH INPUT LATCHES
CD74HC4515E RENESAS

获取价格

 		暂无描述
CD74HC4515E ROCHESTER

获取价格

 		HC/UH SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDIP24
CD74HC4515EE4 TI

获取价格

 		HIGH-SPEED CMOS LOGIC 4-TO-16 LINE DECODER/DEMULTIPLEXER WITH INPUT LATCHES
CD74HC4515EN ROCHESTER

获取价格

 		HC/UH SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDIP24

与CD74HC4514M96相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证