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CD74HC221-W

更新时间： 2024-11-22 02:58:47
品牌 Logo 应用领域
德州仪器 - TI 逻辑集成电路
页数 文件大小 规格书
22页 450K
描述
High-Speed CMOS Logic

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CD74HC221-W 技术参数

是否无铅： 含铅生命周期：Obsolete
包装说明：,Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.58
逻辑集成电路类型：MONOSTABLE MULTIVIBRATORBase Number Matches：1

CD74HC221-W 数据手册

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CD54HC221, CD74HC221,  
CD74HCT221  
Data sheet acquired from Harris Semiconductor  
SCHS166F  
High-Speed CMOS Logic  
Dual Monostable Multivibrator with Reset  
November 1997 - Revised October 2003  
Features  
Description  
• Overriding RESET Terminates Output Pulse  
• Triggering from the Leading or Trailing Edge  
• Q and Q Buffered Outputs  
The ’HC221 and CD74HCT221 are dual monostable  
multivibrators with reset. An external resistor (R ) and an  
X
[ /Title  
(CD74  
HC221  
,
CD74  
HCT22  
1)  
external capacitor (C ) control the timing and the accuracy  
X
for the circuit. Adjustment of R and C provides a wide  
X
X
range of output pulse widths from the Q and Q terminals.  
Pulse triggering on the B input occurs at a particular voltage  
level and is not related to the rise and fall time of the trigger  
pulse.  
• Separate Resets  
• Wide Range of Output-Pulse Widths  
• Schmitt Trigger on B Inputs  
• Fanout (Over Temperature Range)  
Once triggered, the outputs are independent of further trigger  
inputs on A and B. The output pulse can be terminated by a  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads LOW level on the Reset (R) pin. Trailing Edge triggering (A)  
/Sub-  
ject  
and leading-edge-triggering (B) inputs are provided for  
triggering from either edge of the input pulse. On power up,  
the IC is reset. If either Mono is not used each input (on the  
unused device) must be terminated either high or low.  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
(High  
Speed  
CMOS  
Logic  
Dual  
Monos  
table  
Multi-  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
The minimum value of external resistance, R , is typically 500Ω.  
X
• HC Types  
The minimum value of external capacitance, C , is 0pF. The  
X
calculation for the pulse width is t = 0.7 R C at V = 4.5V.  
- 2V to 6V Operation  
W
X X  
CC  
- High Noise Immunity: N = 30%, N = 30% of V  
CC  
IL  
IH  
Ordering Information  
at V  
= 5V  
CC  
o
PART NUMBER  
CD54HC221F3A  
CD74HC221E  
TEMP. RANGE ( C)  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
PACKAGE  
16 Ld CERDIP  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOP  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
CD74HC221M  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
l
OL OH  
CD74HC221MT  
CD74HC221M96  
CD74HC221NSR  
CD74HC221PW  
CD74HC221PWR  
CD74HC221PWT  
CD74HCT221E  
CD74HCT221M  
CD74HCT221MT  
CD74HCT221M96  
Pinout  
CD54HC221  
(CERDIP)  
CD74HC221  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
(PDIP, SOIC, SOP, TSSOP)  
CD74HCT221  
(PDIP, SOIC)  
TOP VIEW  
1A  
1B  
1R  
1Q  
2Q  
1
2
3
4
5
6
7
8
16 V  
CC  
15 1C R  
X
X
NOTE: When ordering, use the entire part number. The suffixes 96  
and R denote tape and reel. The suffix T denotes a small-quantity  
reel of 250.  
14 1C  
X
13 1Q  
12 2Q  
11 2R  
10 2B  
2C  
X
X
2C R  
X
9
2A  
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
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