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CD74HC139M96E4 PDF预览

CD74HC139M96E4

更新时间： 2024-11-23 23:13:35
品牌 Logo 应用领域
德州仪器 - TI 解码器驱动器解复用器逻辑集成电路光电二极管
页数 文件大小 规格书
11页 270K
描述
High-Speed CMOS Logic Dual 2- to 4-Line Decoder/Demultiplexer

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中文翻译

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CD74HC139M96E4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP, SOP16,.25针数：16
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.1
系列：HC/UH输入调节：STANDARD
JESD-30 代码：R-PDSO-G16JESD-609代码：e4
长度：9.9 mm负载电容（CL）：50 pF
逻辑集成电路类型：OTHER DECODER/DRIVER最大I（ol）：0.004 A
湿度敏感等级：1功能数量：2
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C输出极性：INVERTED
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：260电源：2/6 V
Prop。Delay @ Nom-Sup：44 ns传播延迟（tpd）：220 ns
认证状态：Not Qualified座面最大高度：1.75 mm
子类别：Decoder/Drivers最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：4.5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：3.9 mmBase Number Matches：1

CD74HC139M96E4 数据手册

 浏览型号CD74HC139M96E4的Datasheet PDF文件第2页浏览型号CD74HC139M96E4的Datasheet PDF文件第3页浏览型号CD74HC139M96E4的Datasheet PDF文件第4页浏览型号CD74HC139M96E4的Datasheet PDF文件第5页浏览型号CD74HC139M96E4的Datasheet PDF文件第6页浏览型号CD74HC139M96E4的Datasheet PDF文件第7页 
CD54HC139, CD74HC139,  
CD54HCT139, CD74HCT139  
Data sheet acquired from Harris Semiconductor  
SCHS148D  
High-Speed CMOS Logic  
Dual 2- to 4-Line Decoder/Demultiplexer  
September 1997 - Revised October 2003  
Features  
Description  
• Multifunction Capability  
The ’HC139 and ’HCT139 devices contain two independent  
binary to one of four decoders each with a single active low  
enable input (1E or 2E). Data on the select inputs (1A0 and  
1A1 or 2A0 and 2A1) cause one of the four normally high  
outputs to go low.  
- Binary to 1 of 4 Decoders or 1 to 4 Line  
Demultiplexer  
[ /Title  
(CD74  
HC139  
,
CD74  
HCT13  
9)  
• Active Low Mutually Exclusive Outputs  
• Fanout (Over Temperature Range)  
If the enable input is high all four outputs remain high. For  
demultiplexer operation the enable input is the data input.  
The enable input also functions as a chip select when these  
devices are cascaded. This device is functionally the same  
as the CD4556B and is pin compatible with it.  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
/Sub-  
ject  
The outputs of these devices can drive 10 low power  
Schottky TTL equivalent loads. The HCT logic family is  
functionally as well as pin equivalent to the LS logic family.  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
(High  
Speed  
CMOS  
Logic  
Dual  
2-to-4  
Line  
Decod  
• HC Types  
Ordering Information  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30%of V  
IL IH  
at  
CC  
TEMP. RANGE  
o
V
= 5V  
PART NUMBER  
CD54HC139F3A  
CD54HCT139F3A  
CD74HC139E  
( C)  
PACKAGE  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
CC  
• HCT Types  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL  
IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
OL OH  
l
CD74HC139M  
• Memory Decoding, Data Routing, Code Conversion  
CD74HC139MT  
CD74HC139M96  
CD74HCT139E  
CD74HCT139M  
CD74HCT139MT  
CD74HCT139M96  
Pinout  
CD54HC139, CD54HCT139  
(CERDIP)  
CD74HC139, CD74HCT139  
(PDIP, SOIC)  
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel of  
250.  
TOP VIEW  
1E  
1A0  
1A1  
1Y0  
1Y1  
1Y2  
1Y3  
GND  
1
2
3
4
5
6
7
8
16 V  
CC  
15 2E  
14 2A0  
13 2A1  
12 2Y0  
11 2Y1  
10 2Y2  
9
2Y3  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
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