CD74ACT297

更新时间： 2024-11-05 22:40:23

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
12页	198K
描述
DIGITAL PHASE-LOCKED LOOP

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CD74ACT297 数据手册

CD74ACT297

DIGITAL PHASE-LOCKED LOOP

SCHS297A – AUGUST 1998 – REVISED SEPTEMBER 1999

Digital Design Avoids Analog

Compensation Errors

M PACKAGE

(TOP VIEW)

Easily Cascadable for Hlgher Order Loops

Useful Frequency Range

– DC to 110 MHz Typical (K CLK)

– DC to 70 MHz Typical (I/D CLK)

ENCTR

K CLK

I/D CLK

D/U

φA2

Dynamically Variable Bandwidth

Very Narrow Bandwidth Attainable

Power-On Reset

ECPD OUT

XORPD OUT

I/D OUT

GND

10 φB

φA1

Output Capability

– Standand: XORPD OUT, ECPD OUT

– Bus Drlver: I/D OUT

SCR Latch-Up-Resistant CMOS Process

and Circuit Design

Speed of Bipolar FAST /AS/S with

Significantly Reduced Power Consumption

Balanced Propagation Delays

ESD Protectlon Exceeds 2000 V per

MIL-STD-883, Method 3015

Packaged in Small-Outline Integrated

Circuit Package

description

The CD74ACT297 device is designed to provide a simple, cost-effective solution to high-accuracy, digital,

phase-locked-loop applications. These devices contain all the necessary circuits, with the exception of the

divide-by-N counter, to build first-order phase-locked loops as described in Figure 1.

Bothexclusive-OR(XORPD)andedge-controlled(ECPD)phasedetectorsareprovidedformaximumflexibility.

Proper partitioning of the loop function, with many of the building blocks external to the package, makes it easy

for the designer to incorporate ripple cancellation or to cascade to higher order phase-locked loops.

The length of the up/down K counter is digitally programmable according to the K-counter function table. With

A, B, C, and D all low, the K counter is disabled. With A high and B, C, and D low, the K counter is only three

stages long, which widens the bandwidth or capture range and shortens the lock time of the loop. When A, B,

C, and D are programmed high, the K counter becomes 17 stages long, which narrows the bandwidth or capture

range and lengthens the lock time. Real-time control of loop bandwidth by manipulating the A-through-D inputs

can maximize the overall performance of the digital phase-locked loop.

This device performs the classic first-order phase-locked-loop function without using analog components. The

accuracyofthedigitalphase-lockedloop(DPLL)isnotaffectedbyV andtemperaturevariations,butdepends

solely on accuracies of the K clock, I/D clock, and loop propagation delays. The I/D clock frequency and the

divide-by-N modulos determine the center frequency of the DPLL. The center frequency is defined by the

relationship f = I/D clock/2N (Hz).

The CD74ACT297 is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TI is a trademark of Texas Instruments Incorporated.

FAST is a trademark of Fairchild Semiconductor.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...12

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与CD74ACT297相关器件

型号	品牌	获取价格	描述	数据表
CD74ACT297E	RENESAS	获取价格	CD74ACT297E
CD74ACT297EN	ETC	获取价格	Analog IC
CD74ACT297EX	RENESAS	获取价格	CD74ACT297EX
CD74ACT297F	ETC	获取价格	Analog IC
CD74ACT297M	TI	获取价格	DIGITAL PHASE-LOCKED LOOP
CD74ACT297M96	RENESAS	获取价格	CD74ACT297M96
CD74ACT297M96E4	TI	获取价格	Digital Phase-Locked-Loop 16-SOIC -55 to 125
CD74ACT297M96G4	TI	获取价格	SPECIALTY LOGIC CIRCUIT, PDSO16, GREEN, PLASTIC, MS-012AC, SOIC-16
CD74ACT297ME4	TI	获取价格	SPECIALTY LOGIC CIRCUIT, PDSO16, GREEN, PLASTIC, MS-012AC, SOIC-16
CD74ACT299	TI	获取价格	8-INPUT UNIVERSAL SHIFT/STORAGE REGISTER WITH COMMON PARALLEL I/O PINS

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