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CD74ACT109EE4

更新时间： 2024-11-24 05:18:07
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德州仪器 - TI 触发器
页数 文件大小 规格书
10页 338K
描述
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

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CD74ACT109EE4 数据手册

 浏览型号CD74ACT109EE4的Datasheet PDF文件第2页浏览型号CD74ACT109EE4的Datasheet PDF文件第3页浏览型号CD74ACT109EE4的Datasheet PDF文件第4页浏览型号CD74ACT109EE4的Datasheet PDF文件第5页浏览型号CD74ACT109EE4的Datasheet PDF文件第6页浏览型号CD74ACT109EE4的Datasheet PDF文件第7页 
CD54ACT109, CD74ACT109  
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS  
WITH CLEAR AND PRESET  
SCHS327 – JANUARY 2003  
CD54ACT109 . . . F PACKAGE  
CD74ACT109 . . . E OR M PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
Speed of Bipolar F, AS, and S, With  
Significantly Reduced Power Consumption  
1CLR  
1J  
V
CC  
2CLR  
2J  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
Balanced Propagation Delays  
±24-mA Output Drive Current  
– Fanout to 15 F Devices  
1K  
1CLK  
1PRE  
1Q  
2K  
SCR-Latchup-Resistant CMOS Process and  
Circuit Design  
2CLK  
11 2PRE  
Exceeds 2-kV ESD Protection Per  
MIL-STD-883, Method 3015  
10  
9
1Q  
2Q  
2Q  
GND  
description/ordering information  
The ’ACT109 devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset  
(PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE  
and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to  
the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and  
isnotdirectlyrelatedtotherisetimeoftheclockpulse. Followingthehold-timeinterval, dataattheJandKinputs  
can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle  
flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – E  
SOIC – M  
CDIP – F  
Tube  
Tube  
CD74ACT109E  
CD74ACT109M  
CD74ACT109E  
–55°C to 125°C  
ACT109M  
Tape and reel CD74ACT109M96  
Tube CD54ACT109F3A  
CD54ACT109F3A  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUTS  
PRE  
L
CLR  
H
CLK  
X
J
X
X
X
L
K
X
X
X
L
Q
H
L
Q
L
H
L
X
H
†
†
H
L
L
X
H
H
H
↑
L
H
H
H
↑
H
L
L
Toggle  
H
H
↑
H
H
X
Q0  
H
Q0  
L
H
H
↑
H
X
H
H
L
Q0  
Q0  
‡
Unpredictableand unstable condition if both PRE and CLR  
go high simultaneously after both being low at the same  
time  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

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CD74ACT109EE4 替代型号

型号 品牌 替代类型 描述 数据表
CD74ACT109E TI

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 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

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