Datasheet > CD54HCT75

CD54HCT75

更新时间： 2024-11-08 22:03:11

品牌	Logo	应用领域
德州仪器 - TI		锁存器
页数	文件大小	规格书
15页	360K
描述
Dual 2-Bit Bistable Transparent Latch

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数据手册

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CD54HCT75 数据手册

CD54HC75, CD74HC75,

CD54HCT75, CD74HCT75

Data sheet acquired from Harris Semiconductor

SCHS135F

Dual 2-Bit Bistable

Transparent Latch

March 1998 - Revised October 2003

Features

Description

• True and Complementary Outputs

• Buffered Inputs and Outputs

The ’HC75 and ’HCT75 are dual 2-bit bistable transparent

latches. Each one of the 2-bit latches is controlled by

separate Enable inputs (1E and 2E) which are active LOW.

When the Enable input is HIGH data enters the latch and

appears at the Q output. When the Enable input (1E and 2E)

is LOW the output is not affected.

[ /Title

(CD74

HC75,

CD74

HCT75

)

/Sub-

ject

(Dual

2-Bit

Bistabl

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

Ordering Information

• Wide Operating Temperature Range . . . -55 C to 125 C

• Balanced Propagation Delay and Transition Times

TEMP. RANGE

PART NUMBER

CD54HC75F3A

CD54HCT75F3A

CD74HC75E

( C)

PACKAGE

16 Ld CERDIP

16 Ld PDIP

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

-55 to 125

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N = 30%, N = 30% of V

IL IH CC

CD74HC75M

16 Ld SOIC

16 Ld SOP

at V

= 5V

CD74HC75MT

CD74HC75M96

CD74HC75NSR

CD74HC75PW

CD74HC75PWR

CD74HCT75E

CD74HCT75M

CD74HCT75PWT

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V = 0.8V (Max), V = 2V (Min)

IL IH

16 Ld TSSOP

16 Ld PDIP

- CMOS Input Compatibility, I ≤ 1µA at V , V

OL OH

16 Ld SOIC

16 Ld TSSOP

NOTE: When ordering, use the entire part number. The sufﬁxes 96

and R denote tape and reel. The sufﬁx T denotes a small-quantity

reel of 250.

Pinout

CD54HC75, CD54HCT75 (CERDIP)

CD74HC75 (PDIP, SOIC, SOP, TSSOP)

CD74HCT75 (PDIP, SOIC, TSSOP)

TOP VIEW

1Q0

1D0

1D1

16 1Q0

15 1Q1

14 1Q1

13 1E

12 GND

11 2Q0

10 2Q0

2D0

2D1

2Q1

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

12 3 4 5 6 7...15

中文翻译

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与CD54HCT75相关器件

型号	品牌	获取价格	描述	数据表
CD54HCT75E	ETC	获取价格	Logic IC
CD54HCT75EN	ETC	获取价格	Logic IC
CD54HCT75F	ETC	获取价格	Logic IC
CD54HCT75F/3	RENESAS	获取价格	HCT SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, CDIP16
CD54HCT75F3A	TI	获取价格	Dual 2-Bit Bistable Transparent Latch
CD54HCT75F3A	RENESAS	获取价格	IC,LATCH,DUAL,2-BIT,HCT-CMOS,DIP,16PIN,CERAMIC
CD54HCT75H/3	RENESAS	获取价格	HCT SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, UUC16
CD54HCT75H/3A	RENESAS	获取价格	HCT SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, UUC16
CD54HCT75M	ETC	获取价格	Logic IC
CD54HCT85	TI	获取价格	High-Speed CMOS Logic 4-Bit Magnitude Comparator

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