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CD54HCT4024F3A PDF预览

CD54HCT4024F3A

更新时间: 2024-11-29 22:03:27
品牌 Logo 应用领域
德州仪器 - TI 计数器触发器逻辑集成电路
页数 文件大小 规格书
11页 283K
描述
High-Speed CMOS Logic 7-Stage Binary Ripple Counter

CD54HCT4024F3A 技术参数

生命周期:Active零件包装代码:DIP
包装说明:DIP-14针数:14
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:5.46Is Samacsys:N
计数方向:UP系列:HCT
JESD-30 代码:R-GDIP-T14长度:19.56 mm
负载电容(CL):50 pF负载/预设输入:NO
逻辑集成电路类型:BINARY COUNTER最大频率@ Nom-Sup:16000000 Hz
最大I(ol):0.004 A工作模式:ASYNCHRONOUS
位数:7功能数量:1
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
包装方法:TUBE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):0.08 mA
Prop。Delay @ Nom-Sup:50 ns传播延迟(tpd):60 ns
认证状态:Not Qualified筛选级别:38535Q/M;38534H;883B
座面最大高度:5.08 mm子类别:Counters
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:NEGATIVE EDGE宽度:6.67 mm
最小 fmax:16 MHzBase Number Matches:1

CD54HCT4024F3A 数据手册

 浏览型号CD54HCT4024F3A的Datasheet PDF文件第2页浏览型号CD54HCT4024F3A的Datasheet PDF文件第3页浏览型号CD54HCT4024F3A的Datasheet PDF文件第4页浏览型号CD54HCT4024F3A的Datasheet PDF文件第5页浏览型号CD54HCT4024F3A的Datasheet PDF文件第6页浏览型号CD54HCT4024F3A的Datasheet PDF文件第7页 
CD54HC4024, CD74HC4024,  
CD54HCT4024, CD74HCT4024  
Data sheet acquired from Harris Semiconductor  
SCHS202C  
High-Speed CMOS Logic  
7-Stage Binary Ripple Counter  
November 1997 - Revised October 2003  
Features  
Description  
• Fully Static Operation  
• Buffered Inputs  
The ’HC4024 and ’HCT4024 are 7-stage ripple-carry binary  
counters. All counter stages are master-slave flip-flops. The  
state of the stage advances one count on the negative  
transition of each input pulse; a high voltage level on the MR  
line resets all counters to their zero state. All inputs and  
outputs are buffered.  
[ /Title  
(CD74  
HC402  
4,  
CD74  
HCT40  
24)  
/Sub-  
ject  
(High  
Speed  
CMOS  
• Common Reset  
• Negative Edge Clocking  
• Fanout (Over Temperature Range)  
Ordering Information  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
TEMP. RANGE  
o
PART NUMBER  
CD54HC4024F3A  
CD54HCT4024F3A  
CD74HC4024E  
( C)  
PACKAGE  
14 Ld CERDIP  
14 Ld CERDIP  
14 Ld PDIP  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
• HC Types  
CD74HC4024M  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
14 Ld TSSOP  
14 Ld TSSOP  
14 Ld TSSOP  
14 Ld PDIP  
- 2V to 6V Operation  
CD74HC4024MT  
CD74HC4024M96  
CD74HC4024PW  
CD74HC4024PWR  
CD74HC4024PWT  
CD74HCT4024E  
CD74HCT4024M  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
CC  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I 1µA at V , V  
OL OH  
l
14 Ld SOIC  
NOTE: When ordering, use the entire part number. The suffixes 96  
and R denote tape and reel. The suffix T denotes a small-quantity  
reel of 250.  
Pinout  
CD54HC4024, CD54HCT4024  
(CERDIP)  
CD74HC4024  
(PDIP, SOIC, TSSOP)  
CD74HCT4024  
(PDIP, SOIC)  
TOP VIEW  
CP  
1
2
3
4
5
6
7
14  
13 NC  
12 Q ’  
V
CC  
MR  
Q
Q
Q
Q
7
6
5
4
1
11 Q  
2
10 NC  
9
8
Q
3
NC  
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1

CD54HCT4024F3A 替代型号

型号 品牌 替代类型 描述 数据表
CD74HCT4024EE4 TI

完全替代

High-Speed CMOS Logic 7-Stage Binary Ripple Counter
CD74HCT4024E TI

完全替代

High-Speed CMOS Logic 7-Stage Binary Ripple Counter

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