5秒后页面跳转
CD54HCT163 PDF预览

CD54HCT163

更新时间: 2024-01-06 07:29:31
品牌 Logo 应用领域
德州仪器 - TI 计数器
页数 文件大小 规格书
19页 434K
描述
High-Speed CMOS Logic Presettable Counters

CD54HCT163 技术参数

生命周期:Obsolete包装说明:,
Reach Compliance Code:unknown风险等级:5.84
Base Number Matches:1

CD54HCT163 数据手册

 浏览型号CD54HCT163的Datasheet PDF文件第2页浏览型号CD54HCT163的Datasheet PDF文件第3页浏览型号CD54HCT163的Datasheet PDF文件第4页浏览型号CD54HCT163的Datasheet PDF文件第5页浏览型号CD54HCT163的Datasheet PDF文件第6页浏览型号CD54HCT163的Datasheet PDF文件第7页 
CD54/74HC161, CD54/74HCT161,  
CD54/74HC163, CD54/74HCT163  
The CD54HCT161 is obsolete  
and no longer is supplied.  
Data sheet acquired from Harris Semiconductor  
SCHS154D  
High-Speed CMOS Logic  
Presettable Counters  
February 1998 - Revised October 2003  
Two count enables, PE and TE, in each counter are  
provided for n-bit cascading. In all counters reset action  
occurs regardless of the level of the SPE, PE and TE inputs  
(and the clock input, CP, in the ’HC161 and ’HCT161  
types).  
Features  
• ’HC161, ’HCT161 4-Bit Binary Counter,  
Asynchronous Reset  
[ /Title  
(CD74  
HC161  
,
CD74  
HCT16  
1,  
CD74  
HC163  
,
CD74  
HCT16  
3)  
• ’HC163, ’HCT163 4-Bit Binary Counter,  
Synchronous Reset  
If a decade counter is preset to an illegal state or assumes  
an illegal state when power is applied, it will return to the  
normal sequence in one count as shown in state diagram.  
• Synchronous Counting and Loading  
• Two Count Enable Inputs for n-Bit Cascading  
• Look-Ahead Carry for High-Speed Counting  
The look-ahead carry feature simplifies serial cascading of  
the counters. Both count enable inputs (PE and TE) must  
be high to count. The TE input is gated with the Q outputs  
of all four stages so that at the maximum count the terminal  
count (TC) output goes high for one clock period. This TC  
pulse is used to enable the next cascaded stage.  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
Ordering Information  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
TEMP. RANGE  
o
• HC Types  
PART NUMBER  
CD54HC161F3A  
CD54HC163F3A  
CD54HCT163F3A  
CD74HC161E  
( C)  
PACKAGE  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
/Sub-  
ject  
- 2V to 6V Operation  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
(High  
Speed  
CMOS  
Logic  
Preset-  
table  
Counte  
rs)  
/Autho  
r ()  
/Key-  
words  
(High  
Speed  
CMOS  
Logic  
Preset-  
table  
Counte  
rs,  
High  
Speed  
at V  
= 5V  
CC  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
CD74HC161M  
IL  
IH  
- CMOS Input Compatibility, I 1µA at V , V  
OL OH  
l
CD74HC161MT  
CD74HC161M96  
CD74HC163E  
Description  
The ’HC161, ’HCT161, ’HC163, and ’HCT163 are  
presettable synchronous counters that feature look-ahead  
carry logic for use in high-speed counting applications. The  
’HC161 and ’HCT161 are asynchronous reset decade and  
binary counters, respectively; the ’HC163 and ’HCT163  
devices are decade and binary counters, respectively, that  
are reset synchronously with the clock. Counting and  
parallel presetting are both accomplished synchronously  
with the negative-to-positive transition of the clock.  
CD74HC163M  
CD74HC163MT  
CD74HC163M96  
CD74HCT161E  
CD74HCT161M  
CD74HCT161MT  
CD74HCT161M96  
CD74HCT163E  
CD74HCT163M  
CD74HCT163MT  
CD74HCT163M96  
A low level on the synchronous parallel enable input, SPE,  
disables counting operation and allows data at the P0 to P3  
inputs to be loaded into the counter (provided that the  
setup and hold requirements for SPE are met).  
All counters are reset with a low level on the Master Reset  
input, MR. In the ’HC163 and ’HCT163 counters  
(synchronous reset types), the requirements for setup and  
hold time with respect to the clock must be met.  
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel of  
250.  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1

与CD54HCT163相关器件

型号 品牌 获取价格 描述 数据表
CD54HCT163E ETC

获取价格

Logic IC
CD54HCT163EN ETC

获取价格

Logic IC
CD54HCT163F TI

获取价格

High-Speed CMOS Logic Presettable Counters
CD54HCT163F RENESAS

获取价格

IC,COUNTER,UP,4-BIT BINARY,HCT-CMOS,DIP,16PIN,CERAMIC
CD54HCT163F ROCHESTER

获取价格

HCT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16
CD54HCT163F/3 RENESAS

获取价格

HCT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16
CD54HCT163F/3A RENESAS

获取价格

IC HCT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16, CERAMIC, DIP-1
CD54HCT163F/3A ROCHESTER

获取价格

HCT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16, CERAMIC, DIP-16
CD54HCT163F3A ROCHESTER

获取价格

HCT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16
CD54HCT163F3A TI

获取价格

High-Speed CMOS Logic Presettable Counters