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CD54HCT157F3A PDF预览

CD54HCT157F3A

更新时间: 2024-11-19 22:17:35
品牌 Logo 应用领域
德州仪器 - TI 解复用器逻辑集成电路
页数 文件大小 规格书
13页 288K
描述
High-Speed CMOS Logic Quad 2-Input Multiplexers

CD54HCT157F3A 技术参数

生命周期:Active零件包装代码:DIP
包装说明:DIP, DIP16,.3针数:16
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.3系列:HCT
JESD-30 代码:R-GDIP-T16长度:19.56 mm
负载电容(CL):50 pF逻辑集成电路类型:MULTIPLEXER
最大I(ol):0.004 A位数:2
功能数量:4输入次数:2
输出次数:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:TRUE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
包装方法:TUBE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):0.08 mA
Prop。Delay @ Nom-Sup:12 ns传播延迟(tpd):190 ns
认证状态:Not Qualified筛选级别:38535Q/M;38534H;883B
座面最大高度:5.08 mm子类别:Multiplexer/Demultiplexers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:6.92 mmBase Number Matches:1

CD54HCT157F3A 数据手册

 浏览型号CD54HCT157F3A的Datasheet PDF文件第2页浏览型号CD54HCT157F3A的Datasheet PDF文件第3页浏览型号CD54HCT157F3A的Datasheet PDF文件第4页浏览型号CD54HCT157F3A的Datasheet PDF文件第5页浏览型号CD54HCT157F3A的Datasheet PDF文件第6页浏览型号CD54HCT157F3A的Datasheet PDF文件第7页 
The CD54HC158 and  
CD74HC158 are obsolete and  
no longer are supplied.  
CD54/74HC157, CD54/74HCT157,  
CD54/74HC158, CD54/74HCT158  
Data sheet acquired from Harris Semiconductor  
SCHS153C  
High-Speed CMOS Logic  
Quad 2-Input Multiplexers  
September 1997 - Revised October 2003  
Features  
Description  
• Common Select Inputs  
• Separate Enable Inputs  
• Buffered inputs and Outputs  
• Fanout (Over Temperature Range)  
The ’HC157, ’HCT157, ’HC158, and ’HCT158 are quad 2-  
input multiplexers which select four bits of data from two  
sources under the control of a common Select input (S). The  
Enable input (E) is active Low. When (E) is High, all of the  
outputs in the 158, the inverting type, (1Y-4Y) are forced  
High and in the 157, the non-inverting type, all of the outputs  
[ /Title  
(CD74H  
C157,  
CD74H  
CT157,  
CD74H  
C158,  
CD74H  
CT158)  
/Subject  
(High  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
(1Y-4Y) are forced Low, regardless of all other input  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads conditions.  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C Moving data from two groups of registers to four common  
output buses is a common use of these devices. The state of  
the Select input determines the particular register from  
which the data comes. They can also be used as function  
generators.  
• Balanced Propagation Delay and Transition Times  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
• HC Types  
Ordering Information  
- 2V to 6V Operation  
Speed  
- High Noise Immunity: N = 30%, N = 30%of V at  
CC  
TEMP. RANGE  
o
IL  
IH  
PART NUMBER  
CD54HC157F3A  
CD54HCT157F3A  
CD54HCT158F3A  
CD74HC157E  
( C)  
PACKAGE  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
V
= 5V  
CC  
• HCT Types  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I 1µA at V , V  
OL OH  
l
CD74HC157M  
Pinout  
CD74HC157MT  
CD74HC157M96  
CD74HCT157E  
CD74HCT157M  
CD74HCT157MT  
CD74HCT157M96  
CD74HCT158E  
CD54HC157, CD54HCT157, CD54HC158, CD54HCT158  
(CERDIP)  
CD74HC157, CD74HCT157, CD74HC158  
(PDIP, SOIC)  
CD74HCT158  
(PDIP)  
TOP VIEW  
S
1
2
3
4
5
6
7
8
16 V  
15 E  
CC  
1I  
0
1
1I  
14 4I  
13 4I  
0
1
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel of  
250.  
1Y  
2I  
2I  
12 4Y  
0
1
11 3I  
10 3I  
0
1
2Y  
9
3Y  
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1

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