CD54HC280, CD74HC280,
CD54HCT280, CD74HCT280
Data sheet acquired from Harris Semiconductor
SCHS175D
High-Speed CMOS Logic
9-Bit Odd/Even Parity Generator/Checker
November 1997 - Revised October 2003
Features
Description
• Typical Propagation Delay = 17ns at V
o
= 5V,
The ’HC280 and ’HCT280 are 9-bit odd/even parity, generator
checker devices. Both even and odd parity outputs are
available for checking or generating parity for words up to nine
bits long. Even parity is indicated (ΣE output is high) when an
even number of data inputs is high. Odd parity is indicated
(ΣO output is high) when an odd number of data inputs is
high. Parity checking for words larger than 9 bits can be
accomplished by tying the ΣE output to any input of an
additional HC/HCT280 parity checker.
CC
C = 15pF, T = 25 C
L
A
[ /Title
(CD74
HC280
,
• Replaces LS180 Types
• Easily Cascadable
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
CD74
HCT28
0)
/Sub-
ject
(High
Speed
CMOS
Logic
9-Bit
Odd/E
ven
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
Ordering Information
TEMP. RANGE
o
• Significant Power Reduction Compared to LSTTL
Logic ICs
PART NUMBER
CD54HC280F3A
CD54HCT280F3A
CD74HC280E
( C)
PACKAGE
14 Ld CERDIP
14 Ld CERDIP
14 Ld PDIP
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
at V
= 5V
CC
CD74HC280MT
CD74HC280M96
CD74HCT280E
14 Ld SOIC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
14 Ld SOIC
14 Ld PDIP
Parity
V = 0.8V (Max), V = 2V (Min)
IL IH
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.
- CMOS Input Compatibility, I ≤ 1µA at V , V
l
OL OH
Pinout
Functional Diagram
CD54HC280, CD54HCT280
(CERDIP)
8
I0
CD74HC280
(PDIP, SOIC)
CD74HCT280
(PDIP)
9
I1
10
I2
5
∑ EVEN
TOP VIEW
11
I3
12
I6
I7
1
2
3
4
5
6
7
14 V
CC
I4
I5
I6
6
∑ ODD
13
1
13 I5
12 I4
11 I3
10 I2
NC
I8
2
4
I7
I8
GND = 7
= 14
ΣE
V
CC
NC = 3
ΣO
GND
9
8
I1
I0
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1