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CD54ACT163F3A PDF预览

CD54ACT163F3A

更新时间： 2024-11-06 05:09:03
品牌 Logo 应用领域
德州仪器 - TI 计数器触发器逻辑集成电路输出元件
页数 文件大小 规格书
18页 677K
描述
4-BIT SYNCHRONOUS BINARY COUNTERS

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CD54ACT163F3A 技术参数

生命周期：Active零件包装代码：DIP
包装说明：DIP-16针数：16
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
Factory Lead Time：6 weeks风险等级：5.16
Is Samacsys：N其他特性：TCO OUTPUT
计数方向：UP系列：ACT
JESD-30 代码：R-GDIP-T16长度：19.56 mm
负载电容（CL）：50 pF负载/预设输入：YES
逻辑集成电路类型：BINARY COUNTER最大频率@ Nom-Sup：80000000 Hz
最大I（ol）：0.024 A工作模式：SYNCHRONOUS
位数：4功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装等效代码：DIP16,.3
封装形状：RECTANGULAR封装形式：IN-LINE
包装方法：TUBE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V最大电源电流（ICC）：0.08 mA
Prop。Delay @ Nom-Sup：15 ns传播延迟（tpd）：16.5 ns
认证状态：Not Qualified筛选级别：38535Q/M;38534H;883B
座面最大高度：5.08 mm子类别：Counters
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：6.92 mm
最小 fmax：80 MHzBase Number Matches：1

CD54ACT163F3A 数据手册

 浏览型号CD54ACT163F3A的Datasheet PDF文件第2页浏览型号CD54ACT163F3A的Datasheet PDF文件第3页浏览型号CD54ACT163F3A的Datasheet PDF文件第4页浏览型号CD54ACT163F3A的Datasheet PDF文件第5页浏览型号CD54ACT163F3A的Datasheet PDF文件第6页浏览型号CD54ACT163F3A的Datasheet PDF文件第7页 
CD54ACT163, CD74ACT163  
4-BIT SYNCHRONOUS BINARY COUNTERS  
SCHS300B – APRIL 2000 – REVISED MARCH 2003  
CD54ACT163 . . . F PACKAGE  
CD74ACT163 . . . E OR M PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
Internal Look-Ahead for Fast Counting  
Carry Output for n-Bit Cascading  
Synchronous Counting  
CLR  
CLK  
A
V
CC  
RCO  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Synchronously Programmable  
Q
A
B
Q
B
description/ordering information  
C
Q
C
The ’ACT163 devices are 4-bit binary counters.  
These synchronous, presettable counters feature  
an internal carry look-ahead for application in  
high-speed counting designs. Synchronous  
operation is provided by having all flip-flops  
D
Q
D
ENP  
GND  
ENT  
LOAD  
clocked simultaneously so that the outputs change, coincident with each other, when instructed by the  
count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting  
spikes normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the  
four flip-flops on the rising (positive-going) edge of the clock waveform.  
The counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15.  
Presetting is synchronous; therefore, setting up a low level at the load input disables the counter and causes  
the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.  
The clear function is synchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low  
after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. This synchronous clear  
allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The  
active-low output of the gate used for decoding is connected to CLR to synchronously clear the counter to 0000  
(LLLL).  
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without  
additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function.  
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a  
high-level pulse while the count is maximum (9 or 15, with Q high). This high-level overflow ripple-carry pulse  
A
can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the  
level of CLK.  
These devices feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that  
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of  
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the  
stable setup and hold times.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – E  
Tube  
Tube  
CD74ACT163E  
CD74ACT163M  
CD74ACT163M96  
CD54ACT163F3A  
CD74ACT163E  
–55°C to 125°C  
SOIC – M  
CDIP – F  
ACT163M  
Tape and reel  
Tube  
CD54ACT163F3A  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...18

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CD54ACT163F3A 替代型号

型号 品牌 替代类型 描述 数据表
CD74ACT163EE4 TI

完全替代

 4-BIT SYNCHRONOUS BINARY COUNTERS
CD74ACT163E TI

完全替代

 CD54ACT161 CD74ACT161
74ACT163PC FAIRCHILD

功能相似

 Synchronous Presettable Binary Counter

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 		8-Bit Serial-In/Parallel-Out Shift Register
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CD54ACT1643A INTERSIL

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CD54ACT164E ETC

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CD54ACT164EN ETC

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CD54ACT164F ETC

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CD54ACT164F3A TI

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 		8-Bit Serial-In/Parallel-Out Shift Register

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