Datasheet > CD4520BMS

CD4520BMS

更新时间： 2024-11-02 22:40:27

品牌	Logo	应用领域
英特矽尔 - INTERSIL		逻辑集成电路
页数	文件大小	规格书
10页	115K
描述
CMOS Dual Up Counters

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数据手册

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CD4520BMS 数据手册

CD4518BMS,

CD4520BMS

CMOS Dual Up Counters

December 1992

Features

Pinout

CD4518BMS, CD4520BMS

• High Voltage Types (20V Rating)

• CD4518BMS Dual BCD Up Counter

• CD4520BMS Dual Binary Up Counter

TOP VIEW

• Medium Speed Operation

CLOCK A

ENABLE A

Q1A

16 VDD

- 6MHz Typical Clock Frequency at 10V

15 RESET B

14 Q4B

• Positive or Negative Edge Triggering

• Synchronous Internal Carry Propagation

• 100% Tested for Quiescent Current at 20V

• 5V, 10V and 15V Parametric Ratings

Q2A

13 Q3B

Q3A

12 Q2B

Q4A

11 Q1B

10 ENABLE B

• Maximum Input Current of 1µA at 18V Over Full Pack-

RESET A

VSS

age Temperature Range; 100nA at 18V and +25^oC

CLOCK B

• Noise Margin (Over Full Package/Temperature Range)

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• Standardized Symmetrical Output Characteristics

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Speciﬁcations for Description of

‘B’ Series CMOS Devices”

Functional Diagram

Applications

Q1A

Q2A

Q3A

Q4A

• Multistage Synchronous Counting

• Multistage Ripple Counting

• Frequency Dividers

CLOCK A

÷10/÷16

ENABLE A

Description

RESET A

CD4518BMS Dual BCD Up Counter and CD4520BMS Dual

Binary Up Counter each consist of two identical, internally

synchronous 4-stage counters. The counter stages are

D-type ﬂip-ﬂops having interchangeable CLOCK and

ENABLE lines for incrementing on either the positive-going

or negative-going transition. For single unit operation the

ENABLE input is maintained high and the counter advances

on each positive-going transition of the CLOCK. The

counters are cleared by high levels on their RESET lines.

Q1B

Q2B

Q3B

Q4B

CLOCK B

÷10/÷16

ENABLE B

The counter can be cascaded in the ripple mode by connect-

ing Q4 to the enable input of the subsequent counter while

the CLOCK input of the latter is held low.

RESET B

The CD4518BMS and CD4520BMS are supplied in these

16-lead outline packages:

VSS = 8

VDD = 16

Braze Seal DIP

Frit Seal DIP

H4S

H1F

Ceramic Flatpack

*CD4518B Only

*H6P †H6W

†CD4520B Only

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 3342

7-1206

12 3 4 5 6 7...10

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