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CD4520BFMSR PDF预览

CD4520BFMSR

更新时间: 2024-01-20 03:00:10
品牌 Logo 应用领域
瑞萨 - RENESAS 输入元件逻辑集成电路触发器
页数 文件大小 规格书
10页 114K
描述
4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16

CD4520BFMSR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.12
计数方向:UP系列:4000/14000/40000
JESD-30 代码:R-GDIP-T16JESD-609代码:e0
长度:19.05 mm负载电容(CL):50 pF
负载/预设输入:NO逻辑集成电路类型:BINARY COUNTER
最大频率@ Nom-Sup:1500000 Hz最大I(ol):0.00036 A
工作模式:SYNCHRONOUS位数:4
功能数量:2端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5/15 VProp。Delay @ Nom-Sup:878 ns
传播延迟(tpd):756 ns认证状态:Not Qualified
筛选级别:MIL-PRF-38535 Class V座面最大高度:1.2 mm
子类别:Counters标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
总剂量:100k Rad(Si) V触发器类型:POSITIVE EDGE
宽度:7.62 mm最小 fmax:1.11 MHz
Base Number Matches:1

CD4520BFMSR 数据手册

 浏览型号CD4520BFMSR的Datasheet PDF文件第2页浏览型号CD4520BFMSR的Datasheet PDF文件第3页浏览型号CD4520BFMSR的Datasheet PDF文件第4页浏览型号CD4520BFMSR的Datasheet PDF文件第5页浏览型号CD4520BFMSR的Datasheet PDF文件第6页浏览型号CD4520BFMSR的Datasheet PDF文件第7页 
CD4518BMS,  
CD4520BMS  
CMOS Dual Up Counters  
December 1992  
Features  
Pinout  
CD4518BMS, CD4520BMS  
• High Voltage Types (20V Rating)  
• CD4518BMS Dual BCD Up Counter  
• CD4520BMS Dual Binary Up Counter  
TOP VIEW  
• Medium Speed Operation  
CLOCK A  
ENABLE A  
Q1A  
1
2
3
4
5
6
7
8
16 VDD  
- 6MHz Typical Clock Frequency at 10V  
15 RESET B  
14 Q4B  
• Positive or Negative Edge Triggering  
• Synchronous Internal Carry Propagation  
• 100% Tested for Quiescent Current at 20V  
• 5V, 10V and 15V Parametric Ratings  
Q2A  
13 Q3B  
Q3A  
12 Q2B  
Q4A  
11 Q1B  
10 ENABLE B  
• Maximum Input Current of 1µA at 18V Over Full Pack-  
RESET A  
VSS  
age Temperature Range; 100nA at 18V and +25oC  
9
CLOCK B  
• Noise Margin (Over Full Package/Temperature Range)  
- 1V at VDD = 5V  
- 2V at VDD = 10V  
- 2.5V at VDD = 15V  
• Standardized Symmetrical Output Characteristics  
• Meets All Requirements of JEDEC Tentative Standard  
No. 13B, “Standard Specifications for Description of  
‘B’ Series CMOS Devices”  
Functional Diagram  
Applications  
3
4
5
6
Q1A  
Q2A  
Q3A  
Q4A  
• Multistage Synchronous Counting  
• Multistage Ripple Counting  
• Frequency Dividers  
CLOCK A  
1
÷10/÷16  
ENABLE A  
2
C
Description  
R
RESET A  
7
CD4518BMS Dual BCD Up Counter and CD4520BMS Dual  
Binary Up Counter each consist of two identical, internally  
synchronous 4-stage counters. The counter stages are  
D-type flip-flops having interchangeable CLOCK and  
ENABLE lines for incrementing on either the positive-going  
or negative-going transition. For single unit operation the  
ENABLE input is maintained high and the counter advances  
on each positive-going transition of the CLOCK. The  
counters are cleared by high levels on their RESET lines.  
11  
12  
13  
14  
Q1B  
Q2B  
Q3B  
Q4B  
CLOCK B  
9
÷10/÷16  
ENABLE B  
10  
C
R
The counter can be cascaded in the ripple mode by connect-  
ing Q4 to the enable input of the subsequent counter while  
the CLOCK input of the latter is held low.  
RESET B  
15  
The CD4518BMS and CD4520BMS are supplied in these  
16-lead outline packages:  
VSS = 8  
VDD = 16  
Braze Seal DIP  
Frit Seal DIP  
H4S  
H1F  
Ceramic Flatpack  
*CD4518B Only  
*H6P †H6W  
†CD4520B Only  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 3342  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
7-1206  

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