Datasheet > CD4099BMS

CD4099BMS

更新时间： 2024-11-05 14:57:51

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
10页	404K
描述
CMOS 8-Bit Addressable Latch

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中文翻译

获取价格

技术参数
数据手册

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CD4099BMS 技术参数

生命周期：	Transferred	包装说明：	,
Reach Compliance Code：	compliant	风险等级：	5.59
Is Samacsys：	N	逻辑集成电路类型：	D LATCH
Base Number Matches：	1

CD4099BMS 数据手册

DATASHEET

CD4099BMS

CMOS 8-Bit Addressable Latch

FN3333

Rev 0.00

December 1992

Features

Pinout

• High Voltage Type (20V Rating)

• Serial Data Input

CD4099BMS

TOP VIEW

• Active Parallel Output

RESET

DATA

16 VDD

15 Q6

14 Q5

13 Q4

12 Q3

11 Q2

10 Q1

• Storage Register Capability

• Master Clear

• Can Function as Demultiplexer

• 100% Tested for Quiescent Current at 20V

• 5V, 10V and 15V Parametric Ratings

• Standardized Symmetrical Output Characteristics

WRITE DISABLE

VSS

• Maximum Input Current of 1A at 18V Over Full Pack-

age Temperature Range; 100nA at 18V and +25^oC

• Noise Margin (Over Full Package/Temperature Range)

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

Functional Diagram

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Specifications for Description of

‘B’ Series CMOS Devices”

WRITE DISABLE

DATA

Applications

• Multi-Line Decoders

• A/D Converters

DECODER

8 LATCHES

Description

CD4099BMS 8-bit addressable latch is a serial input, parallel

output storage register that can perform a variety of functions.

RESET

Data are inputted to a particular bit in the latch when that bit

is addressed (by means of inputs A0, A1, A2) and when

WRITE DISABLE is at a low level. When WRITE DISABLE is

high, data entry is inhibited; however, all 8 outputs can be

continuously read independent of WRITE DISABLE and

address inputs.

VDD = 16

VSS = 8

A master RESET input is available, which resets all bits to a

logic “0” level when RESET and WRITE DISABLE are at a

high level. When RESET is at a high level, and WRITE DIS-

ABLE is at a low level, the latch acts as a 1 of 8 demulti-

plexer; the bit that is addressed has an active output which

follows the data input, while all unaddressed bits are held to

a logic “0” level.

The CD4099BMS is supplied in these 16-lead outline packages:

Braze Seal DIP

Frit Seal DIP

Ceramic Flatpack

H4X

H1F

H6W

FN3333 Rev 0.00

December 1992

Page 1 of 10

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中文翻译

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