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CD4098BDMS PDF预览

CD4098BDMS

更新时间： 2024-11-05 14:48:23
品牌 Logo 应用领域
瑞萨 - RENESAS 时钟逻辑集成电路
页数 文件大小 规格书
11页 105K
描述
4000/14000/40000 SERIES, DUAL MONOSTABLE MULTIVIBRATOR, CDIP16, DIP-16

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中文翻译

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CD4098BDMS 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：DIP,针数：16
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.08系列：4000/14000/40000
JESD-30 代码：R-CDIP-T16JESD-609代码：e0
逻辑集成电路类型：MONOSTABLE MULTIVIBRATOR数据/时钟输入次数：2
功能数量：2端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
输出极性：COMPLEMENTARY封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE传播延迟（tpd）：500 ns
认证状态：Not Qualified筛选级别：MIL-PRF-38535 Class V
座面最大高度：5.08 mm表面贴装：NO
技术：CMOS温度等级：MILITARY
端子面层：TIN LEAD端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
宽度：7.62 mmBase Number Matches：1

CD4098BDMS 数据手册

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CD4098BMS  
CMOS Dual Monostable Multivibrator  
December 1992  
Features  
Description  
• High Voltage Type (20V Rating)  
CD4098BMS dual monostable multivibrator provides stable  
retriggerable/resettable one shot operation for any fixed volt-  
age timing application.  
• Retriggerable/Resettable Capability  
• Trigger and Reset Propagation Delays Independent of  
RX, CX  
An external resistor (RX) and an external capacitor (CX)  
control the timing for the circuit. Adjustment of RX and CX  
provides a wide range of output pulse widths from the Q and  
Q terminals. The time delay from trigger input to output  
transition (trigger propagation delay) and the time delay from  
reset input to output transition (reset propagation delay) are  
independent of RX and CX.  
• Triggering from Leading or Trailing Edge  
• Q and Q Buffered Outputs Available  
• Separate Resets  
• Wide Range of Output Pulse Widths  
• 100% Tested for Quiescent Current at 20V  
• 5V, 10V and 15V Parametric Ratings  
• Standardized Symmetrical Output Characteristics  
Leading edge triggering (+TR) and trailing edge triggering  
(-TR) inputs are provided for triggering from either edge of  
an input pulse. An unused +TR input should be tied to VSS.  
An unused -TR input should be tied to VDD. A RESET (on  
low level) is provided for immediate termination of the output  
pulse or to prevent output pulses when power is turned on.  
An unused RESET input should be tied to VDD. However, if  
an entire section of the CD4098BMS is not used, its RESET  
should be tied to VSS. See Table 9.  
• Maximum Input Current of 1µA at 18V Over Full Pack-  
age Temperature Range; 100nA at 18V and +25oC  
• Noise Margin (Over Full Package/Temperature Range)  
- 1V at VDD = 5V  
- 2V at VDD = 10V  
In normal operation the circuit triggers (extends the output  
pulse one period) on the application of each new trigger  
pulse. For operation in the non-retriggerable mode, Q is  
connected to -TR when leading edge triggering (+TR) is  
used or Q is connected to +TR when trailing edge triggering  
(-TR) is used.  
- 2.5V at VDD = 15V  
• Meets All Requirements of JEDEC Tentative Standard  
No. 13B, “Standard Specifications for Description of  
‘B’ Series CMOS Devices”  
Applications  
The time period (T) for this multivibrator can be  
approximated by: TX = 1/2RXCX for CX 3 0.01µF. Time  
periods as a function of RX for values of CX and VDD are  
given in Figure 8. Values of T vary from unit to unit and as a  
function of voltage, temperature, and RXCX.  
• Pulse Delay and Timing  
• Pulse Shaping  
Astable Multivibrator  
The minimum value of external resistance, RX, is 5kΩ. The  
maximum value of external capacitance, CX, is 100µF.  
Figure 9 shows time periods as a function of CX for values of  
RX and VDD.  
Pinout  
CD4098BMS  
TOP VIEW  
The output pulse width has variations of ±2.5% typically, over  
the temperature range of -55oC to +125oC for CX = 1000pF  
and RX = 100kΩ.  
CX1  
RXCX (1)  
RESET (1)  
+TR (1)  
-TR (1)  
Q1  
1
2
3
4
5
6
7
8
16 VDD  
For power supply variations of ±5%, the output pulse width  
has variations of ±0.5% typically, for VDD = 10V and 15V  
and ±1% typically, for VDD = 5V at CX = 1000pF and  
RX = 5kΩ.  
15 CX2  
14 RXCX (2)  
13 RESET (2)  
12 +TR (2)  
11 -TR (2)  
10 Q2  
The CD4098BMS is supplied in these 16-lead outline packages:  
Braze Seal DIP  
Frit Seal DIP  
Ceramic Flatpack  
H4T  
H1F  
H6W  
Q1  
9
Q2  
VSS  
TERMINALS 1, 8, 15 ARE ELECTRICALLY  
CONNECTED INTERNALLY  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 3332  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
7-482  
1234567...11

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