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CD4089

更新时间： 2024-11-03 22:54:19
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英特矽尔 - INTERSIL /
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10页 95K
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CMOS Binary Rate Multiplier

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CD4089 数据手册

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CD4089BMS  
CMOS Binary Rate Multiplier  
December 1992  
conjunction with an up/down counter and control logic used  
to perform arithmetic operations (adds, subtract, divide, raise  
to a power), solve algebraic and differential equations,  
generate natural logarithms and trigometric functions, A/D  
and D/A conversions, and frequency division.  
Features  
• High Voltage Type (20V Rating)  
• Cascadable in Multiples of 4 Bits  
• Set to “15” Input and “15” Detect Output  
• 100% Tested for Quiescent Current at 20V  
• 5V, 10V and 15V Parametric Ratings  
• Standardized Symmetrical Output Characteristics  
For words of more than 4 bits, CD4089BMS devices may be  
cascaded in two different modes: an Add mode and a Multi-  
ply mode (see Figures 3 and 4). In the Add mode some of  
the gaps left by the more significant unit at the count of 15  
are filled in by the less significant units. For example, when  
two units are cascaded in the Add mode and programmed to  
11 and 13, respectively, the more significant unit will have 11  
output pulses for every 16 input pulses and the other unit will  
have 13 output pulses for every 256 input pulses for a total of  
• Maximum Input Current of 1µA at 18V Over Full Pack-  
age Temperature Range; 100nA at 18V and +25oC  
• Noise Margin (Over Full Package/Temperature Range)  
- 1V at VDD = 5V  
11  
16  
13  
189  
256  
- 2V at VDD = 10V  
+
=
256  
- 2.5V at VDD = 15V  
In the Multiply mode the fraction programmed into the first  
rate multiplier is multiplied by the fraction programmed into  
the second multiplier. Thus the output rate will be  
• Meets All Requirements of JEDEC Tentative Standard  
No. 13B, “Standard Specifications for Description of  
‘B’ Series CMOS Devices”  
11  
16  
13  
16  
143  
256  
x
=
Applications  
• Numerical Control  
• Instrumentation  
• Digital Filtering  
The CD4089BMS has an internal synchronous 4 bit counter  
which, together with one of the four binary input bits, pro-  
duces pulse trains as shown in Figure 6.  
If more than one binary input bit is high, the resulting pulse  
train is a combination of the separate pulse trains as shown  
in Figure 6.  
• Frequency Synthesis  
Description  
The CD4089BMS is supplied in these 16-lead outline packages:  
CD4089BMS is a low power 4 bit digital rate multiplier that  
provides an output pulse rate that is the clock-input-pulse  
rate multiplied by /16 times the binary input. For example,  
when the binary input number is 13, there will be 13 output  
pulses for every 16 input pulses. This device may be used in  
Braze Seal DIP  
Frit Seal DIP  
Ceramic Flatpack  
H4W  
H2R  
H6P  
1
Functional Diagram  
Pinout  
CD4089BMS  
TOP VIEW  
BINARY RATE  
SELECT INPUTS  
CLOCK  
STROBE  
10  
9
INHIBIT  
B
14 15  
A
C
2
D
3
CASCADE  
12  
“15” OUT  
1
2
3
4
5
6
7
8
16 VDD  
(CARRY) IN  
C
15 B  
OUT  
OUT  
RATE  
RATE  
SELECT  
LOGIC  
11  
6
5
D
14 A  
SET TO  
4 BIT  
“15”  
SET TO “15”  
13 CLEAR  
12 CASCADE  
11 INHIBIT IN (CARRY)  
10 STROBE  
BINARY  
COUNTER  
4
OUT  
OUTPUTS  
OUT  
INHIBIT OUT (CARRY)  
VSS  
CLEAR  
13  
“15” OUT  
1
7
9
CLOCK  
INHIBIT (CARRY) OUT  
VDD = 16  
VSS = 8  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 3329  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
7-1064  
1234567...10

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