Datasheet > CD4078BMS

CD4078BMS

更新时间： 2024-11-28 22:54:19

品牌	Logo	应用领域
英特矽尔 - INTERSIL		栅
页数	文件大小	规格书
8页	70K
描述
CMOS 8 Input NOR/OR Gate

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中文翻译

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数据手册

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CD4078BMS 数据手册

CD4078BMS

CMOS 8 Input NOR/OR Gate

December 1992

CD4078BMS

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Features

• High Voltage Type (20V Rating)

Pinout

• Medium Speed Operation

K **

14 VDD

13 J *

12 H

- tPHL, tPLH = 75ns (Typ.) at VDD = 10V

• Buffered Inputs and Output

• 5V, 10V and 15V Parametric Ratings

• Standardized, Symmetrical Output Characteristics

• 100% Tested for Quiescent Current at 20V

11 G

10 F

VSS

• Maximum Input Current of 1µA at 18V Over Full Pack-

age Temperature Range; 100nA at 18V and +25^oC

• Noise Margin (Over Full Package/Temperature Range)

- 1V at VDD = 5V

**^{K = A + B + C + D + E + F + G + H}

J = A + B + C + D + E + F + G + H

NC = NO CONNECTION

- 2V at VDD = 10V

- 2.5V at VDD = 15V

Functional Diagram

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Speciﬁcations for Description of

‘B’ Series CMOS Devices”

Description

CD4078BMS NOR/OR Gate provides the system designer with

direct implementation of the positive logic 8 input NOR and OR

functions and supplements the existing family of CMOS gates.

The CD4078BMS is supplied in these 14 lead outline packages:

J = A + B + C + D + E + F + G + H

K = A + B + C + D + E + F + G + H

6, 8 = NO CONNECTION

VDD = 14

Braze Seal DIP

Frit Seal DIP

H4Q

H1B

Ceramic Flatpack H3W

VSS = 7

Logic Diagram

FIGURE 1. LOGIC DIAGRAM

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 3326

7-1038

12 3 4 5 6 7 8

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