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CD4081BCN PDF预览

CD4081BCN

更新时间: 2024-10-25 22:54:19
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 98K
描述
Quad 2-Input OR Buffered B Series Gate . Quad 2-Input AND Buffered B Series Gate

CD4081BCN 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP14,.3
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.06
Is Samacsys:N系列:4000/14000/40000
JESD-30 代码:R-PDIP-T14JESD-609代码:e3
长度:19.18 mm负载电容(CL):50 pF
逻辑集成电路类型:AND GATE功能数量:4
输入次数:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5/15 VProp。Delay @ Nom-Sup:250 ns
传播延迟(tpd):250 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:5.08 mm
子类别:Gates最大供电电压 (Vsup):15 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

CD4081BCN 数据手册

 浏览型号CD4081BCN的Datasheet PDF文件第2页浏览型号CD4081BCN的Datasheet PDF文件第3页浏览型号CD4081BCN的Datasheet PDF文件第4页浏览型号CD4081BCN的Datasheet PDF文件第5页浏览型号CD4081BCN的Datasheet PDF文件第6页浏览型号CD4081BCN的Datasheet PDF文件第7页 
October 1987  
Revised January 1999  
CD4071BC • CD4081BC  
Quad 2-Input OR Buffered B Series Gate •  
Quad 2-Input AND Buffered B Series Gate  
General Description  
Features  
Low power TTL compatibility:  
The CD4071BC and CD4081BC quad gates are monolithic  
complementary MOS (CMOS) integrated circuits con-  
structed with N- and P-channel enhancement mode tran-  
sistors. They have equal source and sink current  
capabilities and conform to standard B series output drive.  
The devices also have buffered outputs which improve  
transfer characteristics by providing very high gain.  
Fan out of 2 driving 74L or 1 driving 74LS  
5V–10V–15V parametric ratings  
Symmetrical output characteristics  
Maximum input leakage 1 µA at 15V over full  
temperature range  
All inputs protected against static discharge with diodes to  
VDD and VSS  
.
Ordering Code:  
Order Number Package Number  
Package Description  
CD4071BCM  
CD4071BCN  
CD4081BCM  
CD4081BCN  
M14A  
N14A  
M14A  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Devices are also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagrams  
Pin Assignments for DIP and SOIC  
CD4071B  
CD4081B  
Top View  
Top View  
© 1999 Fairchild Semiconductor Corporation  
DS005977.prf  
www.fairchildsemi.com  

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