Datasheet > CD4077BMS

CD4077BMS

更新时间： 2024-10-25 22:54:19

品牌	Logo	应用领域
英特矽尔 - INTERSIL		逻辑集成电路光电二极管栅
页数	文件大小	规格书
8页	75K
描述
CMOS Quad Exclusive OR and Exclusive NOR Gates

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中文翻译

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数据手册

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CD4077BMS 数据手册

CD4070BMS

CD4077BMS

CMOS Quad Exclusive OR and

Exclusive NOR Gates

December 1992

CD4070BMS

TOP VIEW

Features

Pinouts

• High Voltage Types (20V Rating)

• CD4070BMS - Quad Exclusive OR Gate

• CD4077BMS - Quad Exclusive NOR Gate

14 VDD

13 H

J = A

K = C

12 G

• Medium Speed Operation

11 M = G

10 L = E

- tPHL, tPLH = 65ns (Typ.) at VDD = 10V, CL = 50pF

• 5V, 10V and 15V Parametric Ratings

VSS

• Standardized, Symmetrical Output Characteristics

• 100% Tested for Quiescent Current at 20V

CD4077BMS

TOP VIEW

• Maximum Input Current of 1µA at 18V Over Full Pack-

age Temperature Range; 100nA at 18V and +25^oC

14 VDD

13 H

• Noise Margin (Over Full Package/Temperature Range)

- 1V at VDD = 5V

J = A

K = C

12 G

- 2V at VDD = 10V

11 M = G

10 L = E

- 2.5V at VDD = 15V

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Speciﬁcations for Description of

‘B’ Series CMOS Devices”

VSS

Applications

Functional Diagram

• Logical Comparators

• Parity Generators and Checkers

• Adders/Subtractors

J = A

K = C

M = G

L = E

Description

CD4070BMS contains four independent Exclusive OR gates.

The CD4077BMS contains four independent Exclusive NOR

gates.

VSS = 7

VDD = 14

The CD4070BMS and CD4077BMS provide the system

designer with a means for direct implementation of the

Exclusive OR and Exclusive NOR functions, respectively.

CD4070BMS

The CD4070BMS and CD4077BMS are supplied in these 14

lead outline packages:

Braze Seal DIP

Frit Seal DIP

H4Q

H1B

*H4F

J = A

K = C

Ceramic Flatpack

*CD4070B Only

†H3W

M = G

L = E

†CD4077B Only

CD4077BMS

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 3322

7-455

12 3 4 5 6 7 8

中文翻译

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