Datasheet > CD4073BMS

CD4073BMS

更新时间： 2024-11-03 22:54:19

品牌	Logo	应用领域
英特矽尔 - INTERSIL		逻辑集成电路栅
页数	文件大小	规格书
10页	115K
描述
CMOS AND Gate

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中文翻译

获取价格

数据手册

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CD4073BMS 数据手册

CD4073BMS, CD4081BMS

CD4082BMS

CMOS AND Gate

January 1993

Features

Pinout

CD4073BMS

TOP VIEW

• High-Voltage Types (20V Rating)

• CD4073BMS Triple 3-Input AND Gate

• CD4081BMS Quad 2-Input AND Gate

• CD4082BMS Dual 4-Input AND Gate

14 VDD

• Medium Speed Operation:

- tPLH, tPHL = 60ns (typ) at VDD = 10V

• 100% Tested for Quiescent Current at 20V

K = D • E • F

VSS

10 L = G • H • I

• Maximum Input Current of 1µA at 18V Over Full Pack-

age Temperature Range; 100nA at 18V and +25^oC

J = A • B • C

• Noise Margin (Over Full Package Temperature Range):

- 1V at VDD = 5V

- 2V at VDD = 10V

CD4081BMS

TOP VIEW

- 2.5V at VDD = 15V

• Standardized Symmetrical Output Characteristics

• 5V, 10V and 15V Parametric Ratings

14 VDD

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Speciﬁcations for Description of

‘B’ Series CMOS Devices”

J = A • B

K = C • D

11 M = G • H

10 L = E • F

Description

CD4073BMS, CD4081BMS and CD4082BMS AND gates

provide the system designer with direct implementation of

the AND function and supplement the existing family of

CMOS gates.

VSS

The CD4073BMS, CD4081BMS and CD4082BMS are supplied

in these 14 lead outline packages:

CD4082BMS

TOP VIEW

Braze Seal DIP

Frit Seal DIP

*H4Q †H4H

*H1B

J = A • B • C • D

14 VDD

13 K = E • F • G • H

Ceramic Flatpack

*H3W

*CD4073B, CD4081B †CD4082B

VSS

NC = NO CONNECTION

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 3324

7-433

12 3 4 5 6 7...10

中文翻译

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