Datasheet > CD4072BMS

CD4072BMS

更新时间： 2024-11-03 22:54:19

品牌	Logo	应用领域
英特矽尔 - INTERSIL		逻辑集成电路栅
页数	文件大小	规格书
10页	117K
描述
CMOS OR Gate

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中文翻译

获取价格

数据手册

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CD4072BMS 数据手册

CD4071BMS, CD4072BMS

CD4075BMS

CMOS OR Gate

December 1992

Features

Pinout

CD4071BMS

TOP VIEW

• High-Voltage Types (20V Rating)

• CD4071BMS Quad 2-Input OR Gate

• CD4072BMS Dual 4-Input OR Gate

• CD4075BMS Triple 3-Input OR Gate

14 VDD

J = A + B

K = C + C

• Medium Speed Operation:

- tPHL, tPLH = 60ns (typ) at 10V

11 M = G + H

10 L = E + F

• 100% Tested for Quiescent Current at 20V

• Maximum Input Current of 1µA at 18V Over Full Pack-

age Temperature Range; 100nA at 18V and +25^oC

VSS

• Standardized Symmetrical Output Characteristics

• Noise Margin (Over Full Package Temperature Range):

- 1V at VDD = 5V

CD4072BMS

TOP VIEW

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• 5V, 10V and 15V Parametric Ratings

J = A + B + C + D

14 VDD

13 K = E +F + G + H

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Speciﬁcations for Description of

‘B’ Series CMOS Devices”

Description

VSS

CD4071BMS, CD4072BMS and CD4075BMS OR gates pro-

vide the system designer with direct implementation of the

positive-logic OR function and supplement the existing fam-

ily of CMOS gates.

NC = NO CONNECTION

The CD4071BMS, CD4072BMS and CD4075BMS are supplied

in these 14 lead outline packages:

CD4075BMS

TOP VIEW

Braze Seal DIP

Frit Seal DIP

*H4H †H4Q

H1B

14 VDD

Ceramic Flatpack

*CD4071, CD4072

H3W

†CD4075 Only

K = D + E + F

VSS

10 L = G + H + I

J = A + B + C

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 3323

7-444

12 3 4 5 6 7...10

中文翻译

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CD4072BMW/883B	NSC	获取价格	IC,LOGIC GATE,DUAL 4-INPUT OR,CMOS,FP,14PIN,CERAMIC
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CD4072BPW	TI	获取价格	CMOS OR GATES