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CD4071BMN PDF预览

CD4071BMN

更新时间: 2024-11-03 22:54:19
品牌 Logo 应用领域
美国国家半导体 - NSC 栅极逻辑集成电路光电二极管
页数 文件大小 规格书
8页 184K
描述
Quad 2-Input OR, AND Buffered B Series Gate

CD4071BMN 技术参数

生命周期:Obsolete包装说明:DIP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.09系列:4000/14000/40000
JESD-30 代码:R-PDIP-T14长度:19.18 mm
负载电容(CL):50 pF逻辑集成电路类型:OR GATE
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE传播延迟(tpd):250 ns
认证状态:Not Qualified座面最大高度:5.08 mm
最大供电电压 (Vsup):15 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:7.62 mm
Base Number Matches:1

CD4071BMN 数据手册

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February 1988  
CD4071BM/CD4071BC  
Quad 2-Input OR Buffered B Series Gate  
CD4081BM/CD4081BC  
Quad 2-Input AND Buffered B Series Gate  
General Description  
Features  
Y
Low power TTL  
compatibility  
Fan out of 2 driving 74L  
or 1 driving 74LS  
These quad gates are monolithic complementary MOS  
(CMOS) integrated circuits constructed with N- and P-chan-  
nel enhancement mode transistors. They have equal source  
and sink current capabilities and conform to standard B se-  
ries output drive. The devices also have buffered outputs  
which improve transfer characteristics by providing very  
high gain.  
Y
5V10V15V parametric ratings  
Y
Symmetrical output characteristics  
Maximum input leakage 1 mA at 15V over full tempera-  
ture range  
Y
All inputs protected against static discharge with diodes to  
.
SS  
V
DD  
and V  
Connection Diagrams  
CD4071B Dual-In-Line Package  
TL/F/5977–3  
Top View  
CD4081B Dual-In-Line Package  
TL/F/5977–6  
Top View  
Order Number CD4071B or CD4081B  
C
1995 National Semiconductor Corporation  
TL/F/5977  
RRD-B30M105/Printed in U. S. A.  

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