CD4069UBMS
CMOS Hex Inverter
December 1992
Features
Pinout
CD4069UBMS
TOP VIEW
• High Voltage Types (20V Rating)
• Standardized Symmetrical Output Characteristics
• Medium Speed Operation: tPHL, tPLH = 30ns (typ) at
10V
A
G = A
B
1
2
3
4
5
6
7
14 VDD
13
12 L = F
11
10 K = E
F
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
H = B
C
E
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
I = C
VSS
9
8
D
J = D
Applications
• Logic Inversion
• Pulse Shaping
Functional Diagram
• Oscillators
1
2
• High-Input-Impedance Amplifiers
A
G = A
H = B
I = C
Description
3
4
B
CD4069UBMS types consist of six CMOS inverter circuits.
These devices are intended for all general-purpose inverter
applications where the medium-power TTL-drive and logic-
level conversion capabilities of circuits such as the CD4009
and CD4049 Hex Inverter/Buffers are not required.
5
6
C
9
8
The CD4069UBMS is supplied in these 14 lead outline pack-
ages:
D
J = D
K = E
L = F
11
E
10
12
Braze Seal DIP
Frit Seal DIP
H4H
H1B
VSS = 7
13
Ceramic Flatpack H3W
F
VDD = 14
Schematic Diagram
VDD
VDD
G = A
G
A
1(3, 5, 9, 11, 13)
2(4, 6, 8, 10, 12)
VSS
FIGURE 1. SCHEMATIC DIAGRAM OF 1 OF 6 IDENTICAL INVERTERS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 3321
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-464