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CD4052BCJ

更新时间： 2024-10-31 22:54:19
品牌 Logo 应用领域
美国国家半导体 - NSC 复用器开关复用器或开关信号电路
页数 文件大小 规格书
10页 191K
描述
Single 8-Channel, Dual 4-Channel, Triple 2-Channel Analog Multiplexer/Demultiplexe

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中文翻译

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CD4052BCJ 技术参数

是否Rohs认证：不符合生命周期：Obsolete
包装说明：DIP-16Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.65
Is Samacsys：N模拟集成电路 - 其他类型：DIFFERENTIAL MULTIPLEXER
JESD-30 代码：R-GDIP-T16JESD-609代码：e0
长度：19.43 mm信道数量：4
功能数量：2端子数量：16
标称断态隔离度：40 dB通态电阻匹配规范：10 Ω
最大通态电阻 (Ron)：400 Ω最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装等效代码：DIP16,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5/15 V
认证状态：Not Qualified座面最大高度：5.08 mm
子类别：Multiplexer or Switches最大供电电压 (Vsup)：15 V
最小供电电压 (Vsup)：5 V标称供电电压 (Vsup)：10 V
表面贴装：NO最长断开时间：200 ns
最长接通时间：450 ns切换：BREAK-BEFORE-MAKE
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.62 mm
Base Number Matches：1

CD4052BCJ 数据手册

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October 1989  
CD4051BM/CD4051BC Single 8-Channel Analog  
Multiplexer/Demultiplexer  
CD4052BM/CD4052BC Dual 4-Channel Analog  
Multiplexer/Demultiplexer  
CD4053BM/CD4053BC Triple 2-Channel Analog  
Multiplexer/Demultiplexer  
General Description  
These analog multiplexers/demultiplexers are digitally con-  
trolled analog switches having low ‘‘ON’’ impedance and  
very low ‘‘OFF’’ leakage currents. Control of analog signals  
an inhibit input. Each control input selects one of a pair of  
channels which are connected in a single-pole double-throw  
configuration.  
up to 15V  
p-p  
3–15V. For example, if V  
can be achieved by digital signal amplitudes of  
eb  
e
e
0V and V  
EE  
5V, V  
SS  
5V,  
DD  
Features  
Y
b
a
analog signals from 5V to 5V can be controlled by digi-  
tal inputs of 0–5V. The multiplexer circuits dissipate ex-  
Wide range of digital and analog signal levels: digital  
3–15V, analog to 15V  
p-p  
b
tremely low quiescent power over the full V  
DD  
V
and  
SS  
supply voltage ranges, independent of the logic  
Y
Y
Y
Low ‘‘ON’’ resistance: 80X (typ.) over entire 15V  
sig-  
p-p  
b
V
V
EE  
DD  
b
High ‘‘OFF’’ resistance: channel leakage of  
e
V
EE  
nal-input range for V  
15V  
DD  
state of the control signals. When a logical ‘‘1’’ is present at  
the inhibit input terminal all channels are ‘‘OFF’’.  
g
10 pA  
b
Logic level conversion for digital addressing signals of  
e
EE  
(typ.) at V  
V
10V  
DD  
CD4051BM/CD4051BC is a single 8-channel multiplexer  
having three binary control inputs. A, B, and C, and an inhibit  
input. The three binary signals select 1 of 8 channels to be  
turned ‘‘ON’’ and connect the input to the output.  
b
e
3–15V) to switch analog signals to  
3–15V (V  
DD  
V
SS  
b
e
15 V  
(V  
DD  
V
EE  
15V)  
p-p  
Y
Y
e
Matched switch characteristics: DR  
ON  
5X (typ.) for  
CD4052BM/CD4052BC is a differential 4-channel multiplex-  
er having two binary control inputs, A and B, and an inhibit  
input. The two binary input signals select 1 or 4 pairs of  
channels to be turned on and connect the differential ana-  
log inputs to the differential outputs.  
b
e
V
V
EE  
15V  
Very low quiescent power dissipation under all digital-  
control input and supply conditions: mW (typ.) at  
DD  
1
b
e
b
Binary address decoding on chip  
e
V
V
V
DD  
V
EE  
10V  
DD  
SS  
Y
CD4053BM/CD4053BC is a triple 2-channel multiplexer  
having three separate digital control inputs, A, B, and C, and  
Connection Diagrams  
Dual-In-Line Packages  
CD4052BM/CD4052BC  
CD4051BM/CD4051BC  
CD4053BM/CD4053BC  
TL/F/5662–1  
Order Number CD4051B, CD4052B, or CD4053B  
C
1995 National Semiconductor Corporation  
TL/F/5662  
RRD-B30M105/Printed in U. S. A.  
1234567...10

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