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CD40208BMS

更新时间： 2024-11-02 22:35:11
品牌 Logo 应用领域
英特矽尔 - INTERSIL /
页数 文件大小 规格书
11页 133K
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CMOS 4 x 4 Multiport Register

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CD40208BMS 数据手册

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CD40208BMS  
CMOS 4 x 4 Multiport Register  
December 1992  
Features  
Description  
• High Voltage Types (20V Rating)  
• One Input and Two Output Buses  
• Unlimited Expansion in Bit and Word Directions  
• Data Lines have Latched Inputs  
• 3-State Outputs  
The CD40208BMS is a 4 x 4 multiport register containing  
four 4-bit registers, write address decoder, two separate  
read address decoders, and two 3-state output buses.  
When the ENABLE input is low, the corresponding output  
bus is switched, independently of the clock, to a high imped-  
ance state. The high impedance third state provides the out-  
puts with the capability of being connected to the bus lines in  
a bus organized system without the need for interface or  
pull-up components.  
• Separate Control of Each Bus, Allowing Simultaneous  
Independent Reading of any of Four Registers on Bus  
A and Bus B and Independent Writing Into any of the  
Four Registers  
• 100% Tested for Quiescent Current at 20V  
• Standardized, Symmetrical Output Characteristics  
• 5V, 10V and 15V Parametric Ratings  
When the WRITE ENABLE input is high, all data input lines  
are latched on the positive transition of the CLOCK and the  
data is entered into the word selected by the write address  
lines. When WRITE ENABLE is low, the CLOCK is inhibited  
and no new data is entered. In either case, the contents of  
any word may be accessed via the read address lines inde-  
pendent of the state of the CLOCK input.  
• Maximum Input Current of 1µA at 18V Over Full Pack-  
age-Temperature Range; 100nA at 18V and +25oC  
• Noise Margin (Full Package-Temperature Range):  
- 1V at VDD = 5V  
The CD40208BMS types are supplied in hermetic 24-lead  
dual-in-line ceramic packages (D and F suffixes), 24-lead  
dual-in-line plastic packages (E suffix), 24-lead ceramic flat  
packages (K suffix), and in chip form (H suffix).  
- 2V at VDD = 10V  
- 2.5V at VDD = 15V  
• Meets All Requirements of JEDEC Tentative Stan-  
dards No. 13B, “Standard Specifications for Descrip-  
tion of “B” Series CMOS Devices”  
The CD40208BMS is supplied in these 24-lead outline pack-  
ages:  
Applications  
Braze Seal DIP  
Ceramic Flatpack  
HNZ  
H4P  
• Scratch Pad Memories  
• Arithmetic Units  
• Data Storage  
Functional Diagram  
Pinout  
CD40208BMS  
TOP VIEW  
WRITE  
ENABLE  
ENABLE A  
15  
3
4
Q3B  
Q2B  
1
2
3
4
5
6
7
8
9
24  
VDD  
20  
D0  
Q0  
23 Q1B  
19  
5
6
7
D1  
Q1  
Q2  
Q3  
DATA  
INPUTS  
WORD A  
OUTPUT  
ENABLE A  
Q0A  
22 Q0B  
18  
D2  
D3  
21 ENABLE B  
20 D0  
17  
Q1A  
8
9
WRITE 0  
WRITE 1  
Q2A  
19 D1  
Q3A  
18 D2  
22  
23  
2
Q0  
Q1  
Q2  
Q3  
14  
13  
READ 1A  
READ 0A  
WRITE 0  
WRITE 1  
17 D3  
WORD B  
OUTPUT  
16 CLOCK  
15 WRITE ENABLE  
14 READ 1A  
13 READ 0A  
1
11  
10  
READ 0B 10  
READ 1B 11  
VSS 12  
READ 1B  
READ 0B  
16  
CLOCK  
21  
VDD = 24  
VSS = 12  
ENABLE B  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 3396  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
7-1431  
1234567...11

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