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CD40175BCM PDF预览

CD40175BCM

更新时间: 2024-11-14 22:56:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 61K
描述
Hex D-Type Flip-Flop · Quad D-Type Flip-Flop

CD40175BCM 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:0.150 INCH, MS-012, SOIC-16
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.09
Is Samacsys:N系列:4000/14000/40000
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:9.9 mm负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:2000000 Hz
位数:4功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5/15 V传播延迟(tpd):300 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:FF/Latches最大供电电压 (Vsup):15 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:3.9 mm
最小 fmax:6 MHzBase Number Matches:1

CD40175BCM 数据手册

 浏览型号CD40175BCM的Datasheet PDF文件第2页浏览型号CD40175BCM的Datasheet PDF文件第3页浏览型号CD40175BCM的Datasheet PDF文件第4页浏览型号CD40175BCM的Datasheet PDF文件第5页浏览型号CD40175BCM的Datasheet PDF文件第6页浏览型号CD40175BCM的Datasheet PDF文件第7页 
October 1987  
Revised July 1999  
CD40174BC • CD40175BC  
Hex D-Type Flip-Flop • Quad D-Type Flip-Flop  
General Description  
Features  
The CD40174BC consists of six positive-edge triggered D-  
type flip-flops; the true outputs from each flip-flop are exter-  
nally available. The CD40175BC consists of four positive-  
edge triggered D-type flip-flops; both the true and comple-  
ment outputs from each flip-flop are externally available.  
Wide supply voltage range: 3V to 15V  
High noise immunity: 0.45 VDD (typ.)  
Low power TTL compatibility:  
fan out of 2 driving 74L or 1 driving 74 LS  
Equivalent to MC14174B, MC14175B  
Equivalent to MM74C174, MM74C175  
All flip-flops are controlled by a common clock and a com-  
mon clear. Information at the D inputs meeting the set-up  
time requirements is transferred to the Q outputs on the  
positive-going edge of the clock pulse. The clearing opera-  
tion, enabled by a negative pulse at Clear input, clears all  
Q outputs to logical “0” and Q s (CD40175BC only) to logi-  
cal “1”.  
All inputs are protected from static discharge by diode  
clamps to VDD and VSS  
.
Ordering Code:  
Order Number Package Number  
Package Description  
CD40174BCM  
CD40174BCN  
CD40175BCM  
CD40175BCN  
M16A  
N16E  
M16A  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagrams  
Pin Assignments for DIP and SOIC  
CD40174B  
CD40175B  
Top View  
Top View  
© 1999 Fairchild Semiconductor Corporation  
DS005987  
www.fairchildsemi.com  

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