5秒后页面跳转
CD40162BC PDF预览

CD40162BC

更新时间: 2024-11-13 22:56:43
品牌 Logo 应用领域
美国国家半导体 - NSC 计数器
页数 文件大小 规格书
8页 153K
描述
Decade Counter with Asynchronous Clear

CD40162BC 数据手册

 浏览型号CD40162BC的Datasheet PDF文件第2页浏览型号CD40162BC的Datasheet PDF文件第3页浏览型号CD40162BC的Datasheet PDF文件第4页浏览型号CD40162BC的Datasheet PDF文件第5页浏览型号CD40162BC的Datasheet PDF文件第6页浏览型号CD40162BC的Datasheet PDF文件第7页 
March 1988  
CD40160BM/CD40160BC  
Decade Counter with Asynchronous Clear  
CD40161BM/CD40161BC  
Binary Counter with Asynchronous Clear  
CD40162BM/CD40162BC  
Decade Counter with Synchronous Clear  
CD40163BM/CD40163BC  
Binary Counter with Synchronous Clear  
General Description  
Features  
Y
Wide supply voltage range  
3.0V to 15V  
0.45 V (typ.)  
These (synchronous presettable up) counters are monolith-  
ic complementary MOS (CMOS) integrated circuits con-  
structed with N- and P-channel enhancement mode transis-  
tors. They feature an internal carry look-ahead for fast  
counting schemes and for cascading packages without ad-  
ditional gating.  
Y
High noise immunity  
DD  
Y
Low power TTL  
compatibility  
fan out of 2 driving 74L  
or 1 driving 74LS  
Y
Internal look-ahead for fast counting schemes  
Carry output for N-bit cascading  
Load control line  
Y
Y
Y
Y
A low level at the load input disables counting and causes  
the outputs to agree with the data input after the next posi-  
tive clock edge. The clear function for the CD40162B and  
CD40163B is synchronous and a low level at the clear input  
sets all four outputs low after the next positive clock edge.  
The clear function for the CD40160B and CD40161B is  
asynchronous and a low level at the clear input sets all four  
outputs low, regardless of the state of the clock.  
Synchronously programmable  
Equivalent to MC14160B, MC14161B, MC14162B,  
MC14163B  
Y
Equivalent to MM74C160, MM74C161, MM74C162,  
MM74C163  
Counting is enabled when both count enable inputs are  
high. Input T is fed forward to also enable the carry out. The  
carry output is a positive pulse with a duration approximately  
equal to the positive portion of Q and can be used to en-  
A
able successive cascaded stages. Logic transitions at the  
enable P or T inputs can occur when the clock is high or  
low.  
Connection Diagram  
Dual-In-Line Package  
Order Number CD40160B, CD40161B,  
CD40162B or CD40163B  
TL/F/5986–1  
Top View  
C
1995 National Semiconductor Corporation  
TL/F/5986  
RRD-B30M105/Printed in U. S. A.  

与CD40162BC相关器件

型号 品牌 获取价格 描述 数据表
CD40162BCJ NSC

获取价格

Decade Counter with Asynchronous Clear
CD40162BCJ/A+ TI

获取价格

IC,COUNTER,UP,DECADE,CMOS,DIP,16PIN,CERAMIC
CD40162BCN NSC

获取价格

Decade Counter with Asynchronous Clear
CD40162BCN/A+ ETC

获取价格

Synchronous Up Counter
CD40162BCN/B+ ETC

获取价格

Synchronous Up Counter
CD40162BD TI

获取价格

4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, CDIP16, HERM
CD40162BD/3 ETC

获取价格

Logic IC
CD40162BDMSR RENESAS

获取价格

SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, CDIP16, BRAZE SEALED, DIP-16
CD40162BE TI

获取价格

4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDIP16, PLAS
CD40162BE98 RENESAS

获取价格

CD40162BE98