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CD40162BKMSR PDF预览

CD40162BKMSR

更新时间： 2024-11-14 14:48:23
品牌 Logo 应用领域
瑞萨 - RENESAS 逻辑集成电路触发器
页数 文件大小 规格书
13页 157K
描述
SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, CDFP16, CERAMIC, DFP-16

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CD40162BKMSR 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：DFP包装说明：DFP, FL16,.3
针数：16Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.78
Is Samacsys：N计数方向：UP
JESD-30 代码：R-CDFP-F16JESD-609代码：e0
负载电容（CL）：50 pF负载/预设输入：YES
逻辑集成电路类型：DECADE COUNTER最大频率@ Nom-Sup：2000000 Hz
最大I（ol）：0.00036 A工作模式：SYNCHRONOUS
位数：4功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：DFP封装等效代码：FL16,.3
封装形状：RECTANGULAR封装形式：FLATPACK
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5/15 V
Prop。Delay @ Nom-Sup：608 ns传播延迟（tpd）：540 ns
认证状态：Not Qualified筛选级别：MIL-PRF-38535 Class V
座面最大高度：2.92 mm子类别：Counters
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：FLAT
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED总剂量：100k Rad(Si) V
触发器类型：POSITIVE EDGE宽度：6.73 mm
最小 fmax：1.48 MHzBase Number Matches：1

CD40162BKMSR 数据手册

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CD40160BMS, CD40161BMS, CD40162BMS,  
CD40163BMS  
December 1992  
File Number 3358  
CMOS Synchronous Programmable 4-Bit  
Counters  
Features  
• High-Voltage Types (20V Rating)  
• CD40160BMS Decade with Asynchronous Clear  
• CD40161BMS Binary with Asynchronous Clear  
• CD40162BMS Decade with Synchronous Clear  
• CD40163BMS Binary with Synchronous Clear  
• Internal Look-Ahead for Fast Counting  
CD40160BMS,  
CD40161BMS,  
CD40162BMS  
and  
CD40163BMS are 4-bit synchronous programmable  
counters. The CLEAR function of the CD40162BMS and  
CD40163BMS is synchronous and a low level at the CLEAR  
input sets all four outputs low on the next positive CLOCK  
edge. The CLEAR function of the CD40160BMS and  
CD40161BMS is asychronous and a low level at the CLEAR  
input sets all four outputs low regardless of the state of the  
CLOCK, LOAD, or ENABLE inputs. A low level at the LOAD  
input disables the counter and causes the output to agree  
with the setup data after the next CLOCK pulse regardless of  
the conditions of the ENABLE inputs.  
• Carry Output for Cascading  
• Synchronously Programmable  
• Clear Asynchronous Input (CD40160BMS, CD40161BMS)  
• Clear Synchronous Input (CD40162BMS, CD40163BMS)  
• Synchronous Load Control Input  
• Low Power TTL Compatibility  
The carry look-ahead circuitry provides for cascading counters  
for n-bit synchronous applications without additional gating.  
Instrumental in accomplishing this function are two count-enable  
inputs and a carry output (COUT). Counting is enabled when  
both PE and TE inputs are high. The TE input is fed forward to  
enable COUT. This enabled output produces a positive output  
pulses with a duration approximately equal to the positive portion  
of the Q1 output. This positive overflow carry pulse can be used  
to enable successive cascaded stages. Logic transitions at the  
PE or TE inputs may occur when the clock is either high or low.  
• Standardized Symmetrical Output Characteristics  
• 100% Tested for Quiescent Current at 20V  
• Maximum Input Current of 1µA at 18V Over Full Package  
o
Temperature Range; 100nA at 18V and +25 C  
• Noise Margin (Over Full Package Temperature Range):  
-
-
-
1V at VDD = 5V  
2V at VDD = 10V  
2.5V at VDD = 15V  
The CD40160BMS through CD40163BMS types are functionally  
equivalent to and pin-compatible with the TTL counter series  
74LS160 through 74LS163 respectively.  
• 5V, 10V and 15V Parametric Ratings  
• Meets All Requirements of JEDEC Tentative Standard No. 13B,  
“Standard Specifications for Description of ‘B’ Series CMOS  
Devices”  
The CD40160BMS, CD40161BMS, CD40162BMS and  
CD40163BMS are supplied in these 16 lead outline packages:  
Applications  
• Programmable Binary and Decade Counting  
CD40160 CD40161 CD40162 CD40163  
Braze Seal DIP  
Frit Seal DIP  
H4W  
H1F  
H6P  
H4X  
H1F  
H6W  
H4X  
H1L  
H6P  
H4W  
H1F  
• Counter Control/Timers  
• Frequency Dividing  
Ceramic Flatpack  
H6W  
Pinout  
Functional Diagram  
CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS  
TOP VIEW  
7
10  
1
14  
13  
PE  
TE  
Q1  
Q2  
CLEAR  
CLOCK  
P1  
1
2
3
4
5
6
7
8
16 VDD  
15 CARRY OUT  
14 Q1  
CLEAR  
LOAD  
CLOCK  
P1  
9
12  
2
Q3  
Q4  
P2  
13 Q2  
3
P3  
12 Q3  
11  
15  
4
P2  
P4  
11 Q4  
5
P3  
10 TE  
PE  
6
VDD = 16  
VSS = 8  
CARRY  
OUT  
P4  
9
LOAD  
VSS  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
4-1  
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