Datasheet > CD40161BKMSR

CD40161BKMSR

更新时间： 2024-11-15 09:04:51

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
13页	157K
描述
4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDFP16

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数据手册

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CD40161BKMSR 数据手册

CD40160BMS, CD40161BMS, CD40162BMS,

CD40163BMS

December 1992

File Number 3358

CMOS Synchronous Programmable 4-Bit

Counters

Features

• High-Voltage Types (20V Rating)

• CD40160BMS Decade with Asynchronous Clear

• CD40161BMS Binary with Asynchronous Clear

• CD40162BMS Decade with Synchronous Clear

• CD40163BMS Binary with Synchronous Clear

• Internal Look-Ahead for Fast Counting

CD40160BMS,

CD40161BMS,

CD40162BMS

and

CD40163BMS are 4-bit synchronous programmable

counters. The CLEAR function of the CD40162BMS and

CD40163BMS is synchronous and a low level at the CLEAR

input sets all four outputs low on the next positive CLOCK

edge. The CLEAR function of the CD40160BMS and

CD40161BMS is asychronous and a low level at the CLEAR

input sets all four outputs low regardless of the state of the

CLOCK, LOAD, or ENABLE inputs. A low level at the LOAD

input disables the counter and causes the output to agree

with the setup data after the next CLOCK pulse regardless of

the conditions of the ENABLE inputs.

• Carry Output for Cascading

• Synchronously Programmable

• Clear Asynchronous Input (CD40160BMS, CD40161BMS)

• Clear Synchronous Input (CD40162BMS, CD40163BMS)

• Synchronous Load Control Input

• Low Power TTL Compatibility

The carry look-ahead circuitry provides for cascading counters

for n-bit synchronous applications without additional gating.

Instrumental in accomplishing this function are two count-enable

inputs and a carry output (COUT). Counting is enabled when

both PE and TE inputs are high. The TE input is fed forward to

enable COUT. This enabled output produces a positive output

pulses with a duration approximately equal to the positive portion

of the Q1 output. This positive overflow carry pulse can be used

to enable successive cascaded stages. Logic transitions at the

PE or TE inputs may occur when the clock is either high or low.

• Standardized Symmetrical Output Characteristics

• 100% Tested for Quiescent Current at 20V

• Maximum Input Current of 1µA at 18V Over Full Package

Temperature Range; 100nA at 18V and +25 C

• Noise Margin (Over Full Package Temperature Range):

1V at VDD = 5V

2V at VDD = 10V

2.5V at VDD = 15V

The CD40160BMS through CD40163BMS types are functionally

equivalent to and pin-compatible with the TTL counter series

74LS160 through 74LS163 respectively.

• 5V, 10V and 15V Parametric Ratings

• Meets All Requirements of JEDEC Tentative Standard No. 13B,

“Standard Specifications for Description of ‘B’ Series CMOS

Devices”

The CD40160BMS, CD40161BMS, CD40162BMS and

CD40163BMS are supplied in these 16 lead outline packages:

Applications

• Programmable Binary and Decade Counting

CD40160 CD40161 CD40162 CD40163

Braze Seal DIP

Frit Seal DIP

H4W

H1F

H6P

H4X

H1F

H6W

H4X

H1L

H6P

H4W

H1F

• Counter Control/Timers

• Frequency Dividing

Ceramic Flatpack

H6W

Pinout

Functional Diagram

CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS

TOP VIEW

CLEAR

CLOCK

16 VDD

15 CARRY OUT

14 Q1

CLEAR

LOAD

CLOCK

13 Q2

12 Q3

11 Q4

10 TE

VDD = 16

VSS = 8

CARRY

OUT

LOAD

VSS

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

4-1

12 3 4 5 6 7...13

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与CD40161BKMSR相关器件

型号	品牌	获取价格	描述	数据表
CD40161BM	NSC	获取价格	Decade Counter with Asynchronous Clear
CD40161B-MIL	TI	获取价格	具有异步清零功能的 CMOS 同步可编程 4 位二进制计数器
CD40161BMJ	NSC	获取价格	Decade Counter with Asynchronous Clear
CD40161BMJ/883	ETC	获取价格	Synchronous Up Counter
CD40161BMN	NSC	获取价格	Decade Counter with Asynchronous Clear
CD40161BMS	INTERSIL	获取价格	CMOS Synchronous Programmable 4-Bit Counters
CD40161BMW	ETC	获取价格	Synchronous Up Counter
CD40161BMW/883	ETC	获取价格	Synchronous Up Counter
CD40161BMW-MIL	TI	获取价格	暂无描述
CD40161BNSR	TI	获取价格	CMOS Synchronous Programmable 4-Bit Counters

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