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CD4014BCN

更新时间: 2024-11-03 22:56:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 移位寄存器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
7页 69K
描述
8-Stage Static Shift Register

CD4014BCN 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.56
Is Samacsys:N其他特性:OUTPUTS ALSO AVAILABLE AT 6TH AND 7TH STAGE OF THE SHIFT REGISTER
计数方向:RIGHT系列:4000/14000/40000
JESD-30 代码:R-PDIP-T16JESD-609代码:e0
长度:19.305 mm逻辑集成电路类型:PARALLEL IN SERIAL OUT
最大频率@ Nom-Sup:2800000 Hz位数:8
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5/15 V
传播延迟(tpd):320 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:Shift Registers
最大供电电压 (Vsup):15 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:7.62 mm最小 fmax:8 MHz
Base Number Matches:1

CD4014BCN 数据手册

 浏览型号CD4014BCN的Datasheet PDF文件第2页浏览型号CD4014BCN的Datasheet PDF文件第3页浏览型号CD4014BCN的Datasheet PDF文件第4页浏览型号CD4014BCN的Datasheet PDF文件第5页浏览型号CD4014BCN的Datasheet PDF文件第6页浏览型号CD4014BCN的Datasheet PDF文件第7页 
October 1987  
Revised January 1999  
CD4014BC  
8-Stage Static Shift Register  
All inputs are protected against static discharge with diodes  
General Description  
to VDD and VSS  
.
The CD4014BC is an 8-stage parallel input/serial output  
shift register. A parallel/serial control input enables individ-  
ual JAM inputs to each of 8 stages. Q outputs are available  
from the sixth, seventh and eighth stages. All outputs have  
equal source and sink current capabilities and conform to  
standard “B” series output drive.  
Features  
Wide supply voltage range: 3.0V to 15V  
High noise immunity: 0.45 VDD (typ.)  
Low power TTL compatibility: Fan out of 2 driving 74L  
or 1 driving 74LS  
When the parallel/serial control input is in the logical “0”  
state, data is serially shifted into the register synchronously  
with the positive transition of the clock. When the parallel/  
serial control input is in the logical “1” state, data is jammed  
into each stage of the register synchronously with the posi-  
tive transition of the clock.  
5V–10V–15V parametric ratings  
Symmetrical output characteristics  
Maximum input leakage:  
1 µA at 15V over full temperature range  
Ordering Code:  
Order Number  
CD4014BCM  
CD4014BCN  
Package Number  
M16A  
Package Description  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide  
N16E  
Devices also available in Tape and Reel. Specify by appending the suffix letter “x” to the ordering code.  
Connection Diagram  
Truth Table  
Pin Assignments for DIP  
Parallel/  
Serial  
Control  
CL  
Serial  
Q1  
(Internal)  
Qn  
PI 1 PI n  
(Note 1) Input  
X
X
X
X
0
1
1
1
1
0
0
X
0
1
0
0
1
1
X
X
X
0
1
0
0
0
0
1
1
1
1
X
X
X
0
Qn1  
Qn1  
Qn  
1
1
X
Q1  
X = Don't care case  
No Change  
Note 1: Level change  
Top View  
© 1999 Fairchild Semiconductor Corporation  
DS005947.prf  
www.fairchildsemi.com  

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